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ADE3700

Line Lock PLL

LLK_PLL_LOCK_TOL

0x0819

R/W

[7:0]

0x20

More than lock_line_nb lines with a phase

error less than the lock_tol will set the lock

status bit, and the pll will work with the lock

time constant.

One or more lines with a phase error more

than lock_tol will reset the lock status bit,

and the pll will work with the slow time

constant.

LSB of lock tol is approx. 200ps.

LLK_PLL_LOCK_LINE_NB

0x081A

R/W

[7:0]

0x30

LLK_PLL_PH_OFFSET

0x081B

R/W

[7:0]

0x0

Phase adjustment.

The maximum phase offset value is equal

to phase_rate[31:21] or 0x40, whichever is

higher.

LLK_PLL_PH_OFFSET_EN

0x081C

R/W

[7]

0x0

phase enable

[6]

skip pulse

[5]

skip pulse at every rising edge of hsync

[4:0]

Reserved

LLK_PLL_PULSE_HIGH_EXT

0x081D

R/W

[7]

0x0

0: no pulse extend

1: extend pulse (normal)

[6:3]

Reserved

R/W

[2:0]

0x0

pulse extend amount

0x0: minimum

0x7: maximum (normal)

LLK_PLL_STAT_LINES_L

0x081E

R/W

[7:0]

0x10

Number of lines to statistically analyze.

LLK_PLL_STAT_LINES_H

0x081F

R/W

[7:0]

LLK_PLL_STAT_ERROR_INC_LO

0x0820

[7:0]

Reserved

LLK_PLL_FINE_ERROR_WAIT

0x0821

[7:4]

Reserved

R/W

[3:0]

0x0

Wait this number of CTRL_CLK cycles

before updating the PLL.

LLK_PLL_STAT_ON_VSYNC

0x0822

[7:2]

Reserved

R/W

[1]

0x0

PLL statistic synchronize on falling edge of

vsync

R/W

[0]

0x0

PLL statistic synchronize on rising edge of

vsync

LLK_PLL_MFACTOR_SHADOW_L

0x0823

R/W

[7:0]

0x80

Number of clocks in a line.

LLK_PLL_MFACTOR_SHADOW_U

0x0824

R/W

[7:0]

0x02

Registers 0x0803 and 0x0802 are

transferred to those registers according to

update_on_venab_fe.

Table 7: Line Lock PLL Registers (Sheet 3 of 4)

Addr

Mode

Bits

Default

Description

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