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TMS320C31PQL60 数据表(PDF) 33 Page - Texas Instruments

部件名 TMS320C31PQL60
功能描述  DIGITAL SIGNAL PROCESSORS
PDF  48 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320C31PQL60 数据表(HTML) 33 Page - Texas Instruments

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TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
33
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
serial-port timing parameters for TMS320C31-40 and TMS320LC31-40 (see Figure 25 and Figure 26)
NO.
’C31-40
’LC31-40
UNIT
MIN
MAX
54
td(H1H-SCK)
Delay time, H1 high to internal CLKX/R
13
ns
55
t (SCK)
Cycle time CLKX/R
CLKX/R ext
tc(H)x2.6
ns
55
tc(SCK)
Cycle time, CLKX/R
CLKX/R int
tc(H)x2
tc(H)x232
ns
56
t (SCK)
Pulse duration CLKX/R high/low
CLKX/R ext
tc(H)+10
ns
56
tw(SCK)
Pulse duration, CLKX/R high/low
CLKX/R int
[tc(SCK)/2]–5
[tc(SCK)/2]+5
ns
57
tr(SCK)
Rise time, CLKX/R
7
ns
58
tf(SCK)
Fall time, CLKX/R
7
ns
59
td(C DX)
Delay time CLKX to DX valid
CLKX ext
30
ns
59
td(C-DX)
Delay time, CLKX to DX valid
CLKX int
17
ns
60
t
(DR CLKRL)
Setup time DR before CLKR low
CLKR ext
9
ns
60
tsu(DR-CLKRL)
Setup time, DR before CLKR low
CLKR int
21
ns
61
th(CLKRL DR)
Hold time DR from CLKR low
CLKR ext
9
ns
61
th(CLKRL-DR)
Hold time, DR from CLKR low
CLKR int
0
ns
62
td(C FSX)
Delay time CLKX to internal FSX high/low
CLKX ext
27
ns
62
td(C-FSX)
Delay time, CLKX to internal FSX high/low
CLKX int
15
ns
63
t
(FSR CLKRL)
Setup time FSR before CLKR low
CLKR ext
9
ns
63
tsu(FSR-CLKRL)
Setup time, FSR before CLKR low
CLKR int
9
ns
64
th(SCKL FS)
Hold time FSX/R input from CLKX/R low
CLKX/R ext
9
ns
64
th(SCKL-FS)
Hold time, FSX/R input from CLKX/R low
CLKX/R int
0
ns
65
t
(FSX C)
Setup time external FSX before CLKX
CLKX ext
–[tc(H)–8]† [tc(SCK)/2]–10†
ns
65
tsu(FSX-C)
Setup time, external FSX before CLKX
CLKX int
[tc(H)–21]†
tc(SCK)/2†
ns
66
td(CH DX)V
Delay time, CLKX to first DX bit, FSX
CLKX ext
30†
ns
66
td(CH-DX)V
y,
,
precedes CLKX high
CLKX int
18†
ns
67
td(FSX-DX)V
Delay time, FSX to first DX bit, CLKX precedes FSX
30†
ns
68
td(CH-DXZ)
Delay time, CLKX high to DX high impedance following last data
bit
17†
ns
† This value is characterized but not tested



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