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TMS320C31PQL60 数据表(PDF) 38 Page - Texas Instruments |
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TMS320C31PQL60 数据表(HTML) 38 Page - Texas Instruments |
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38 / 48 page ![]() TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS SPRS035B – MARCH 1996 – REVISED JANUARY 1999 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 data-rate timing modes (continued) CLKX/R FSX(INT) FSX(EXT) DX FSR DR 62 65 64 63 60 61 59 68 67 66 Bit 0 Bit n-2 Bit n-3 Bit n-2 Bit n-3 Bit n-1 Bit n-1 NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed data-rate mode. Figure 26. Timing for Variable Data-Rate Mode |
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