TMS320C31, TMS320LC31

DIGITAL SIGNAL PROCESSORS

SPRS035B – MARCH 1996 – REVISED JANUARY 1999

28

POST OFFICE BOX 1443

timing parameters for RESET for the TMS320C31 and TMS320LC31 (continued)

CLKIN

H1

H3

38

39

42

45

46

49

48

41

40

43

RESET

(see Notes A and B)

IACK

Ten H1 Clock Cycles

D

(see Note C)

A

(see Note C)

Control Signals

(see Note D)

Asynchronous

Reset Signals

(see Note A)

44

47

TMS320C31 R/W

(see Note E)

NOTES: A. Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.

B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact

sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.

C. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the

reset vector is fetched twice, with no software wait states.

D. Control signals include STRB.

E. The R/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally

18–22 k

Ω, if undesirable spurious writes are caused when these outputs go low.

Figure 21. Timing for RESET

5

10 15 20

25 30 35 40 45 50 55

60 65 70 75 80 85 90

95 100

0

0

2

4

6

8

10

12

14

16

18

20

22

Case Temperature (

°C)

TMS320C31-40 (Extended Temperature)

TMS320C31-40

4.75 V

≤ VDD ≤ 5.25 V

105 110 115 120 125

Extended

Temperature

Range

Figure 22. CLKIN to H1 and H3 as a Function of Temperature