TMS320C31, TMS320LC31

DIGITAL SIGNAL PROCESSORS

SPRS035B – MARCH 1996 – REVISED JANUARY 1999

42

POST OFFICE BOX 1443

changing the peripheral pin I/O modes

The following tables show the timing parameters for changing the peripheral pin from a general-purpose output

pin to a general-purpose input pin and vice versa. The numbers shown in Figure 29 and Figure 30 correspond

to those shown in the NO. column of the tables below.

timing parameters for peripheral pin changing from general-purpose output to input mode

(see Note 8 and Figure 29)

NO.

’LC31-33

’C31-40

’LC31-40

’C31-50

’C31-60

’C31-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

84

th(H1H)

Hold time, peripheral pin after

H1 high

15

13

10

8

6

ns

85

tsu(GPIO-H1L)

Setup time, peripheral pin

before H1 low

10

9

9

8

7

ns

86

th(H1L-GPIO)

Hold time, peripheral pin after

H1 low

0

0

0

0

0

ns

NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents

of internal-control registers associated with each peripheral.

86

85

84

Value on Pin

Seen in

Peripheral-

Control

Register

Synchronizer Delay

Buffers Go

From

Output to

Input

Execution

of Store of

Peripheral-

Control

Register

Data Bit

Peripheral

Pin

(see Note A)

I/O

Control Bit

H1

H3

Output

Data

Seen

Data

Sampled

NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.

Figure 29. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode