TMS320C31PQL60 datasheet(21/48 Pages) TI

21 / 48 page

TMS320C31, TMS320LC31

DIGITAL SIGNAL PROCESSORS

SPRS035B – MARCH 1996 – REVISED JANUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

XF0 and XF1 timing when executing LDFI or LDII

The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII. The

numbers shown in Figure 15 correspond with those in the NO. column of the tables below.

timing parameters for XF0 and XF1 when executing LDFI or LDII for TMS320C31 (see Figure 15)

NO.

’LC31-33

’C31-40

’LC31-40

’C31-50

’C31-60

’C31-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

td(H3H-XF0L)

Delay time, H3 high to XF0 low

tsu(XF1-H1L)

Setup time, XF1 before H1 low

th(H1L-XF1)

Hold time, XF1 after H1 low

STRB

R/W

RDY

XF0 Pin

XF1 Pin

Fetch

LDFI or LDII

Decode

Read

Execute

Figure 15. Timing for XF0 and XF1 When Executing LDFI or LDII

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