TMS320C31, TMS320LC31

DIGITAL SIGNAL PROCESSORS

SPRS035B – MARCH 1996 – REVISED JANUARY 1999

43

POST OFFICE BOX 1443

timing parameters for peripheral pin changing from general-purpose input to output mode

(see Note 8 and Figure 30)

NO.

’LC31-33

’C31-40

’LC31-40

’C31-50

’C31-60

’C31-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

87

td(H1H-GPIO)

Delay time, H1 high to

peripheral pin switching

from input to output

15

13

10

8

6

ns

NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents

of internal-control registers associated with each peripheral.

Peripheral

Pin

(see Note A)

I/O

Control

Bit

H1

H3

Execution of Store

of Peripheral-

Control Register

87

NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.

Figure 30. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode