TMS320C31, TMS320LC31

DIGITAL SIGNAL PROCESSORS

SPRS035B – MARCH 1996 – REVISED JANUARY 1999

41

POST OFFICE BOX 1443

general-purpose I/O timing

Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The contents of the internal

control registers associated with each peripheral define the modes for these pins.

peripheral pin I/O timing

The table, timing parameters for peripheral pin general-purpose I/O, defines peripheral pin general-purpose I/O

timing parameters. The numbers shown in Figure 28 correspond with those in the NO. column of the table

below.

timing parameters for peripheral pin general-purpose I/O (see Note 8 and Figure 28)

NO.

LC31-33

’C31-40

’LC31-40

’C31-50

’C31-60

’C31-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

81

tsu(GPIO-H1L)

Setup time,

general-purpose input

before H1 low

12

10

9

8

7

ns

82

th(H1L-GPIO)

Hold time,

general-purpose input

after H1 low

0

0

0

0

0

ns

83

td(H1H-GPIO)

Delay time,

general-purpose output

after H1 high

15

13

10

8

6

ns

NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents

of internal-control registers associated with each peripheral.

Peripheral

Pin

(see Note A)

H1

H3

83

83

81

82

NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.

Figure 28. Timing for Peripheral Pin General-Purpose I/O