TMS320C31, TMS320LC31

DIGITAL SIGNAL PROCESSORS

SPRS035B – MARCH 1996 – REVISED JANUARY 1999

22

POST OFFICE BOX 1443

The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. The number

shown in Figure 16 corresponds with the number in the NO. column of the table below.

timing parameters for XF0 when executing STFI or STII (see Figure 16)

NO.

’LC31-33

’C31-40

’LC31-40

’C31-50

’C31-60

’C31-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

28

td(H3H-XF0H)

Delay time, H3 high to XF0

high

15

13

12

11

8

ns

† XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of

the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store

from executing, the address of the store will not be driven until the store can execute.

H3

H1

STRB

R/W

A

D

RDY

XF0 Pin

Fetch

STFI or STII

Read

Execute

28

Decode

Figure 16. Timing for XF0 When Executing an STFI or STII