TMS320C31, TMS320LC31

DIGITAL SIGNAL PROCESSORS

SPRS035B – MARCH 1996 – REVISED JANUARY 1999

12

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)

PARAMETER

TEST CONDITIONS

’C31

’LC31

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP‡

MAX

MIN

TYP‡

MAX

UNIT

VOH

High-level output voltage

VDD = MIN, IOH = MAX

2.4

3

2

V

VOL

Low-level output voltage

VDD = MIN, IOH = MAX

0.3

0.6

0.4

V

IZ

High-impedance current

VDD = MAX

– 20

+ 20

– 20

+ 20

µA

II

Input current

VI = VSS to VDD

– 10

+ 10

– 10

+ 10

µA

IIP

Input current (with internal

pullup)

Inputs with internal pullups§

– 600

20

– 600

10

µA

¶#

f = 33 MHz

’LC31 33

150

325

120

250

¶#

fx = 33 MHz ’LC31-33

150

325

120

250

¶#

T25

°C

fx = 33 MHz

’C31-33

(ext. temp)

150

325

ICC

Supply current¶#

TA = 25°C,

VDD = MAX

fx = 40 MHz ’C31-40

160

390

150

300

mA

CC

y

VDD = MAX

fx = 50 MHz ’C31-50

200

425

fx = 60 MHz ’C31-60

225

475

fx = 80 MHz ’C31-80

275

550

IDD

Supply current

Standby,

IDLE2

Clocks shut off

50

20

µA

Ci

Input

All inputs except CLKIN

15||

15||

pF

Ci

capacitance

CLKIN

25

25

pF

Co

Output capacitance

20||

20||

pF

† All input and output voltage levels are TTL compatible.

‡ For ’C31, all typical values are at VDD = 5 V, TA (air temperature) = 25°C. For ’LC31, all typical values are at VDD = 3.3 V,

TA (air temperature) = 25°C.

§ Pins with internal pullup devices: INT3 – INT0, MCBL / MP.

¶ Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which

are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the

maximum rate possible. See

Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020).

# fx is the input clock frequency.

|| Specified by design but not tested

NOTE 6: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS

clock.