memory read/write timing

The following table defines memory read/write timing parameters for STRB. The numbers shown in Figure 12 and Figure 13 correspond with

those in the NO. column of the table below.

NO.

’LC31-33

’C31-40

’LC31-40

’C31-50

’C31-60

’C31-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

12

td(H1L-SL)

Delay time, H1 low to STRB low

0‡

10

0‡

6

0‡

5

0‡

5

0‡

5

ns

13

td(H1L-SH)

Delay time, H1 low to STRB high

0‡

10

0‡

6

0‡

5

0‡

5

0‡

5

ns

14

td(H1H-RWL)R

Delay time, H1 high to R/W low (read)

0‡

10

0‡

9

0‡

7

0‡

6

0‡

4

ns

15

td(H1L-A)

Delay time, H1 low to A valid

0‡

14

0‡

11

0‡

9

0‡

8

0‡

7

ns

16

tsu(D-H1L)R

Setup time, D before H1 low (read)

16

14

10

9

8

ns

17

th(H1L-D)R

Hold time, D after H1 low (read)

0

0

0

0

0

ns

18

tsu(RDY-H1H)

Setup time, RDY before H1 high

8

8

6

5

4

ns

19

th(H1H-RDY)

Hold time, RDY after H1 high

0

0

0

0

0

ns

20

td(H1H-RWH)W

Delay time, H1 high to R/W high (write)

10

9

7

6

4

ns

21

tv(H1L-D)W

Valid time, D after H1 low (write)

20

17

14

12

8

ns

22

th(H1H-D)W

Hold time, D after H1 high (write)

0

0

0

0

0

ns

23

td(H1H-A)W

Delay time, H1 high to A valid on back-to-back write

cycles (write)

18

15

12

10

8

ns

24

td(A-RDY)

Delay time, RDY from A valid

8‡

7‡

6‡

6‡

P - 8§

ns

24A

Taa

Address valid to data valid (read)

30

25

21

16

10

ns

† See Figure 14 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT = 80 pF).

‡ This value is characterized but not tested

§ In earlier data sheets, this parameter was shown as an “at speed” value. It is in fact a synchronized signal and therefore relative to Tc(H) where P = tc(C1) = tc(H)/2.