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ST7MC1 数据表(PDF) 189 Page - STMicroelectronics |
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ST7MC1 数据表(HTML) 189 Page - STMicroelectronics |
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189 / 308 page  ST7MC1/ST7MC2 189/308 MOTOR CONTROLLER (Cont’d) 10.6.9 Channel Manager The channel manager consists of: – A Phase State register with preload and polarity function – A multiplexer to direct the PWM to the low and/ or high channel group – A tristate buffer asynchronously driven by an emergency input The block diagram is shown in Figure 108. Figure 108. Channel Manager Block Diagram CFF[2:0] bits OO bits* C OE[5:0] bits 6 6 OS[2:0] bits* Phasen Register* SR bit 3 PWM generator Sampling frequency DAC bit Channel [5:0] Current comparator output V I PWM Generator SQ R V0C1 bit V I Filter OP[5:0] bits MOE bit x6 x6 6 1 MPHST Register MPOL Register MCRB Register MPAR Register * = Preload register, changes taken into account at next C event. MCRA Register MCRA Register MCRA Register MCRA Register MCFR Register Reg C DS,H Z events: Commutation BEMF Zero-crossing End Of Demagnetization E Emergency Stop Notes: Updated/Shifted on R Ratio Updated (+1 or -1) Multiplier Overflow R+/- O Current Mode Voltage Mode I V Regn Updated with Regn+1 on C 1 2 Branch taken after C event Branch taken after D event Channel [5:0] Dead Time Dead Time Dead Time 8 MDTG Register 2 6 High frequency chopper HFE[1:0] bits HFRQ[2:0] bits MREF Register 5 CLI bit CLIM bit OCV bit 1 1 1 OFF time Sensorless Sensor Sampling Clock “1” 1 |
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