ST7MC1 datasheet(190/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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MOTOR CONTROLLER (Cont’d)

10.6.9.1 MPHST Phase State Register

A preload register enables software to asynchro-

nously update the channel configuration for the

next step (during the previous commutation inter-

rupt routine for example): the OO[5:0] bits in the

MPHST register are copied to the Phase register

on a C event.

Table 49. Output State

Direct access to the phase register is also possible

when the DAC bit in the MCRA register is set.

Note: In Direct Access Mode (DAC bit is set in

MCRA register):

1: A C event is generated as soon as there is a

write access to OO[5:0] bits in MPHST register,

2: The PWM application is selected by the OS0 bit

in the MCRB register,

3: Regardless of the value of the CKE bit in the

MCRA register, the MTIM Clock is disabled and D

and Z events are not detected.

Table 50. DAC and MOE Bit Meaning

*Note: The reset state of the outputs can be either

high impedance, low or high state depending on

the corresponding option bit.

The polarity register is used to match the polarity

of the power drivers keeping the same control log-

ic and software. If one of the OPx bits in the MPOL

MCOx is VDD.

Each output status depends also on the momen-

tary state of the PWM, its group (low or high), and

the peripheral state.

PWM Features

The outputs can be split in two PWM groups in or-

der to differentiate the high side and the low side

switches. This output property can be pro-

grammed using the OE[5:0] bits in the MPAR reg-

ister.

Table 51. Meaning of the OE[5:0] Bits

The multiplexer directs the PWM to the upper

channel, the lower channel or both of them alter-

natively or simultaneously according to the periph-

eral state.

This means that the PWM can affect any of the up-

per or lower channels allowing the selection of the

most appropriate reference potential when free-

wheeling the motor in order to:

– Improve system efficiency

– Speed up the demagnetization phase

– Enable Back EMF zero crossing detection.

The OS[2:0] bits in the MCRB register allow the

PWM configuration to be configured for each case

as shown in Figure 110 and Figure 109.

During demagnetization, the OS2 bit is used to

control PWM mode, and it is latched in a preload

event occurs and the configuration is active imme-

diately.

The OS1 bit is used to control the PWM between

the D and Z events to control back-emf detection.

OS0 bit will allow to control the PWM signal be-

tween Z event and next C event.

Note about demagnetization speed-up: during

demagnetization the voltage on the winding has to

be as high as possible in order to reduce the de-

magnetization time. Software can apply a different

PWM configuration on the outputs between the C

and D events, to force the free wheeling on the ap-

propriate diodes to maximize the demagnetization

voltage.

10.6.9.2 Emergency Feature

When the NMCES pin goes low

– The tristate output buffer is put in reset state

asynchronously

– The MOE bit in the MCRA register is reset

– An interrupt request is sent to the CPU if the EIM

bit in the MIMR register is set

This bit can be connected to an alarm signal from

the drivers, thermal sensor or any other security

component.

This feature functions even if the MCU oscillator is

off.

OP[5:0] bit

OO[5:0] bit

MCO[5:0] Pin

1 (OFF)

0-(PWM allowed)

0 (OFF)

1-(PWM allowed)

MOE

bit

DAC

bit

Effect on Output

Reset state*

Standard

running mode

MPHST register value (depending on

MPOL, MPAR register values and

PWM setting) see Table 74

OE[5:0]

Channel group

High channel

Low channel

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