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ST7MC1 数据表(PDF) 211 Page - STMicroelectronics

部件名 ST7MC1
功能描述  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI
PDF  308 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7MC1 数据表(HTML) 211 Page - STMicroelectronics

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MOTOR CONTROLLER (Cont’d)
CONTROL REGISTER B (MCRB)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7= Reserved, must be kept at reset value.
Bit 6= CPB*: Compare Bit for Zero-crossing detec-
tion.
0: Zero crossing detection on falling edge
1: Zero crossing detection on rising edge
Bit 5= HDM*: Hardware Demagnetization event
Mask bit
0: Hardware Demagnetization disabled
1: Hardware Demagnetization enabled
Bit 4= SDM*: Simulated Demagnetization event
Mask bit
0: Simulated Demagnetization disabled
1: Simulated Demagnetization enabled
Bit 3 = OCV: Over Current Handling in Voltage
mode
0: Over Current protection is OFF
1:Over current protection is ON
This bit acts as follows
Table 60. Over current handling
Note 1: This feature is also available when using
the three PWM outputs (PCN bit=1 in the MDTG
register), providing that the VOC1bit = 0 (MCRA
register). See section 10.6.8.2 on page 185
Bits 2:0 = OS2*, OS[1:0]: Operating output mode
Selection bits
Refer to the Step behaviour diagrams (Figure 109,
Figure 110) and Table 61, “Step Behaviour/ sen-
sorless mode,” on page 211.
These bits are used to define the various PWM
output configurations.
Note: OS2 is the only preload bit.
Table 61. Step Behaviour/ sensorless mode
Note: For more details, see Step behaviour dia-
grams (Figure 109 and Figure 110).
* Preload bits, new value taken into account at the
next C event. A C event is generated at each write
to MPHST in Direct Access mode.
76
54
32
10
0
CPB*
HDM*
SDM*
OCV
OS2*
OS1
OS0
CLIM bit CLI bit OCV bit
Output effect
Interrupt
00
x
Normal running
mode
No
01
x
PWM is put off as
Current loop effect
No
10
x
Normal running
mode
No
11
0
PWM is put off as
Current loop effect
Yes
11
1
All MCOx outputs
are put in reset
state (MOE reset) 1)
Yes
OS2
bit
PWM after
C and
before D
OS1
bit
PWM after
D and
before Z
OS0
PWM after
Z and
before next
C
0
On High
Channels
0
On High
Channels
0
On high
channels
1
On low
channels
1
On Low
Channels
0
On high
channels
1
On low
channels
1
On Low
Channels
0
On High
Channels
0
On high
channels
1
On low
channels
1
On Low
Channels
0
On high
channels
1
On low
channels
1



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