ST7MC1 datasheet(219/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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MOTOR CONTROLLER (Cont’d)

COMPARE PHASE U PRELOAD REGISTER

HIGH (MCPUH)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = CPUH[7:0] Most Significant Byte of

phase U preload value

COMPARE PHASE U PRELOAD REGISTER

LOW (MCPUL)

Read/Write Read/Write (except bits 2:0)

Reset Value: 0000 0000 (00h)

Bits 7:5 = CPUL[7:3] Low bits of phase U preload

value.

Bits 2:0 = Reserved.

COMPARE

PRELOAD

HIGH

(MCP0H)

Read/Write (except bits 7:4)

Reset Value: 0000 1111 (0Fh)

Bits 7:4 = Reserved.

Bits 3:0 = CP0H[3:0] Most Significant Bits of Com-

pare 0 preload value.

COMPARE

PRELOAD

LOW

(MCP0L)

Read/Write

Reset Value: 1111 1111 (FFh)

Bits 7:0 = CP0L[7:0] Low byte of Compare 0

preload value.

Note 1: The 16-bit Compare registers MCMPOx,

MCMPUx, MCMPVx, MCMPWx MSB and LSB

parts have to be written sequentially before being

taken into account when an update event occurs;

refer to section 10.6.10.4 on page 200 for details.

Note 2: The CPB, HDM, SDM, OS2 bits in the

MCRB and the bits OE[5:0] are marked with *. It

means that these bits are taken into account at the

following commutation event (in normal mode) or

when a value is written in the MPHST register

when in direct access mode. For more details, re-

fer to the description of the DAC bit in the MCRA

the registers to be updated at the same time.

Warning: Access to Preload registers

Special care has to be taken with Preload regis-

ters, especially when using the ST7 BSET and

BRES instructions on MTC registers.

For instance, while writing to the MPHST register,

you will write the value in the preload register.

However, while reading at the same address, you

will get the current value in the register and not the

value of the preload register.

Excepted for three-phase PWM generator’s regis-

ters, all preload registers are loaded in the active

registers at the same time. In normal mode this is

done automatically when a C event occurs, how-

ever in direct access mode (DAC bit=1) the

preload registers are loaded as soon as a value is

written in the MPHST register.

Caution: Access to write-once bits

Special care has to be taken with write-once bits in

MPOL and MDTG registers; these bits have to be

accessed first during the set-up. Any access to the

other bits (not write-once) through a BRES or a

BSET instruction will lock the content of write-once

bits (no possibility for the core do distinguish indi-

vidual bit access: Read/write internal signal acts

on a whole register only). This protection is then

only unlocked after a processor hardware reset.

CPUH

CPUL7 CPUL6 CPUL5 CPUL4 CPUL3

----

CP0H3

CP0H2

CP0H1

CP0H0

CP0L7 CP0L6 CP0L5 CP0L4 CP0L3 CP0L2 CP0L1 CP0L0

ST7MC1 数据表(PDF) 219 Page - STMicroelectronics

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