ST7MC1 datasheet(220/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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MOTOR CONTROLLER (Cont’d)

DEAD TIME GENERATOR REGISTER (MDTG)

Read/Write (except bits 5:0 write once-only)

Reset Value: 1111 1111 (FFh)

Bit 7 = PCN: Number of PWM Channels .

0: Only PWM U signal is output to the PWM man-

ager for six-step mode motor control (e.g. PM

BLDC motors)

1: The three PWM signals U, V and W are output

to the channel manager (e.g. for three-phase

sinewave generation)

Bit 6 = DTE*: Dead Time Generator Enable

0: Disable the Dead Time generator

1: Enable the Dead Time generator and apply

complementary PWM signal to the adjacent

switch

* write once-only bit if PCN bit is set, read/write if

PCN bit is reset. To clear the DTE bit if PCN=1,

it is mandatory to clear the PCN bit first.

Table 74. DeadTime generator set-up

Note 1: This table is true on condition that the CKE

bit is set (Peripheral clock enabled) and the MOE

bit is set (MCOx outputs enabled). See Table 56,

“Output configuration summary,” on page 209

When the PCN bit is reset (e.g. for PM BLDC mo-

tors), in Direct Access mode (DAC=1), if the DTE

bit is reset, PWM signals can be applied on the

MCOx outputs but not complementary PWM. Of

course, logical levels can be also applied on the

outputs.

If the DTE bit is set (PCN=0 and DAC=1), chan-

nels are paired and complementary PWM signals

can be output on the MCOx pins. This will follow

the rules detailed in Table 53, “Dead Time genera-

tor outputs,” on page 196 as the channels are

grouped in pairs.

In this case, the PWM application is selected by

the OS0 bit in the MCRB register.

It is also possible to add a chopper on the PWM

signal output using bits HFE[1:0] and HFRQ[2:0] in

the MREF register.

Caution 1: The PWM mode will be selected via

the 00[5:0] bits in the MPHST register, the OE[5:0]

bits in the MPAR register and the OS2 and OS0

bits in the MCRB register as shown in Table 62,

“PWM mode when SR=1,” on page 212.

Caution 2: When driving motors with three inde-

pendent pairs of complementary PWM signals

(PCN=1),

disabling

the

deadtime

generator

(DTE=0) causes the deadtime to be null: high and

low side signals are exactly complemented.

It is therefore recommended not to disable the

deadtime generator (it may damage the power

stage), unless deadtimes are inserted externally.

Bits 5:0 = DTG[5:0]* Dead time generator set-up.

These bits set-up the deadtime duration and reso-

lution. Refer to Table 52, “Dead time programming

and example,” on page 194 for details.

With Fmtc = 16MHz dead time values range from

125ns to 16µs with steps of 125ns, 250ns and

500ns.

* Write-once bits; once write-accessed these bits

cannot be re-written unless the processor is reset

(See “Caution: Access to write-once bits” on

page 219.).

PCN

DTE

DTG5

DTG4

DTG3

DTG2

DTG1

DTG0

DAC

PCN bit

in MDTG

DTE bit

in MDTG

Complementary PWM

applied to adjacent

switch

YES

YES, but

WITHOUT deadtime

NO Complementary

PWM

YES

YES, but

WITHOUT deadtime

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