ST72734 datasheet(63/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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SYNC PROCESSOR (SYNC) (Cont’d)

4.4.6.5 Example of VSYNCO extraction for a

negative composite sync with serration pulses

Refer to Figure 43.

In extraction mode, the 5-bit comparator checks

the counter value with respect to the threshold.

When the incoming signal is high, the counter is

increased, otherwise it is decreased.

When the counter reaches the threshold on its way

down, VSYNCO is asserted. During the vertical

blanking, the counter value is decreased down to a

programmable minimum, i.e. it does not underflow.

When the vertical period is finished, the counter

starts counting up and when the maximum is

reached, VSYNCO is negated. The extracted

signal may be validated by software since it is input

to Timer ICAP1.

Serration pulses during vertical blanking can be

filtered if the serration pulse widths are less than

8µs.

In the same way, positive composite sync signals

can be used by properly selecting the edge

sensitivity in HSYNCI width measurement mode

(LCV0 bit).

Figure 43. VSYNCO Extraction from a Composite Signal (negative polarity)

Figure 44. Obtaining the 11-bit Vertical Period (V11BITS)

VR01990

8µs

Composite signal

Input

Max Pulse width: 8µs

1F-Threshold

Counter value:

1F=Max

Serration pulses

VSYNCO Pulse

Max Delay: 8µs

or threshold

HSYNCO

Threshold

0=Min

VSYNCO

generated

VGENR

CFGR

V11BITS

Example:

VGENR=CCh, CFGR = 3h

V11bits=663h

Q’2 Q’1 Q’0

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