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DDC INTERFACE (Cont’d)

4.8.5 DDC Standard

The DDC standard is divided in several data

transfer protocols: DDC1, DDC2B, DDC/CI.

For DDC1/2B, refer to the “VESA DDC Standard

v3.0” specification. For DDC/CI refer to the “VESA

DDC Commands Interface v1.0”

– DDC1 is a uni-directional transmission of EDID

v1 (128 bytes) from display to host clocked by

VSYNCI.

– DDC2B is a uni-directional channel from display

to host. The host computer uses base-level I2C

commands to read the EDID data from the dis-

play which is always in slave mode.

Specific types of display contain EDID at fixed

I2C device addresses within the device (refer to

Table 25).

– DDC/CI is a bi-directional channel between the

host computer and the display. The DDC/CI of-

fers a display control interface based on I2C bus.

It includes the DDC2Bi and DDC2AB standards.

Note: The DDC2AB standard is no longer handled by the

interface.

4.8.5.1 DDC1/2B Interface

4.8.5.1.1 Functionnal description

Refer to the DCR, AHR registers in Section 4.8.6.

for the bit definitions.

The DDC1/2B Interface acts as an I/O interface

between a DDC bus and the microcontroller

memory. In addition to receiving and transmitting

serial data, this interface directly transfers parallel

data to and from memory using a DMA engine,

only halting CPU activity for two clock cycles

during each byte transfer.

The interface supports by hardware:

– Two DDC communication protocols called DDC1

and DDC2B.

– Write operations into RAM.

– Read operations from RAM.

In DDC1, the interface reads sequential EDID v1

data bytes from the microcontroller memory, and

transmits them on SDA synchronized with Vsync.

In DDC2B mode, it operates in I2C slave mode.

The DDC1/2B Interface supports several DDC

versions configured using the CF[2:0] bits in the

DCR register which can only be changed while the

interface is disabled (HWPE bit=0 in the DCR

version is used and which Device Addresses are

recognized.

Depending on the DDC version, one or two device

address

pairs

will

recognized

and

the

corresponding EDID structure will be validated

(refer to Table 25):

– DDC v2 (CF2=0,CF1=0,CF0=0): DDC1 is ena-

bled and device addresses A0h/A1h are recog-

nized. EDID v1 is used.

– DDC v2 (CF2=1,CF1=0,CF0=0): DDC1 is disa-

bled and device addresses A0h/A1h are recog-

nized. EDID v1 is used.

– Plug and Display (CF2=0,CF1=0,CF0=1):

DDC1 is disabled and device addresses A2h/

A3h are recognized. EDID v2 is used.

– Plug and Display + DDC v2 (CF2=0,CF1=1,

CF0=0): DDC1 is enabled and device addresses

A0h/A1h and A2h/A3h are recognized. Both

EDID structures v1 and v2 are used.

– Plug and Display + DDC v2 (CF2=1,CF1=1,

CF0=0): DDC1 is disabled and device addresses

A0h/A1h and A2h/A3h are recognized. Both

EDID structures v1 and v2 are used.

– FPDI (CF2=0,CF1=1, CF0=1): DDC1 is disabled

and device addresses A6h/A7h are recognized.

EDID v2 is used.

Table 25. Valid Device Addresses and EDID structure

Device Address

CF2 bit

CF1 bit

CF0 bit

Transfer Type

EDID v1:

A0h / A1h = 1010 000x

128-byte EDID structure write/read

EDID v2:

A2h / A3h = 1010 001x

001

256-byte EDID structure write/read

010

110

EDID v2:

A6h / A7h = 1010 011x

256-byte EDID structure write/read

reserved

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