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ST72734 数据表(PDF) 29 Page - STMicroelectronics |
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ST72734 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 144 page ![]() ST72774/ST727754/ST72734 29/144 Figure 16. Input Structure for SYNC signals 4.1.3 Port A PA7 and PA[2:0] can be defined as Input lines (with pull-up) or as Push-pull Outputs. PA [6:3] can be defined as Input lines (without pull- up) or as Output Open drain lines. PA7 and PA[2:0] can be defined as Input lines (with pull-up) or as Push-pull Outputs. PA [6:3] can be defined as Input lines (without pull- up) or as Output Open drain lines. Table 8. Port A Description Pin HSYNCI Input I/O logic (if existing) TTL trigger (no pull-up) Pin CSYNCI Input I/O logic (if existing) TTL trigger pull-up VDD VSYNCI Input HFBACK Input VFBACK Input PORT A I / O Alternate Function Input* Output Signal Condition PA0 With pull-up push-pull OCMP1 OC1E =1 (CR2[TIMER]) PA1 With pull-up push-pull - - PA2 With pull-up push-pull VSYNCI2 VSYNCSEL=1 (MISCR) PA3 Without pull-up open-drain - - PA4 Without pull-up open-drain - - PA5 Without pull-up open-drain - - PA6 Without pull-up open-drain - - PA7 With pull-up push-pull BLANKOUT BLKEN = 1 (ENR[SYNC]) *Reset State |
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