ST72734 datasheet(68/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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SYNC PROCESSOR (SYNC) (Cont’d)

4.4.10 Register Description

CONFIGURATION REGISTER (CFGR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = HACQ Horizontal Sync Analyzer Mode

Set by software, reset by hardware when the

measurement is done. The sync generator must

be disabled (HVGEN=0).

0 : Measurement is done, the result can be read

in HGENR.

1: Start measuring HSYNCO/HFBACK low lev-

el.

Bit 6 = VACQ Vertical Sync Analyzer Mode

Set by software, reset by hardware when the

measurement is done. The sync generator must

be disabled (HVGEN=0).

0: Measurement is done, and the result can be

read in VGENR.

1: Start measuring the number of scan lines dur-

ing VSYNCO/VFBACK low level.

Bit 5 = Reserved. Must be cleared.

Bit 4 = 2FHINH Inhibition of Pre/Post equalization

pulses.

This

function

removes

pre/post

equalization

pulses on HSYNCO signal. The sync generator

and the Horizontal sync analyzer must both be

disabled (HVGEN=HACQ=0).

0: Disable

1: Enable

Bit 3 = VEXT VSYNCO pulse width extension in

case of post-equalization pulses.

The sync generator and the Horizontal and

Vertical sync analyzer must be disabled (HVGEN

= 0, HACQ = 0, VACQ = 0, VCORDIS=0). Vertical

extension must be enabled (VGENR > 0

0: Disable

1: Enable

Bits 2:0 = Q’2..Q’0

These are the read/write LSB of the VGENR 11-bit

counter. Refer to Figure 44.

HACQ VACQ

2FHINH VEXT

Q’2

Q’1

Q’0

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