ST72734 datasheet(81/144 Pages) STMICROELECTRONICS

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USB INTERFACE (Cont’d)

PID REGISTER (PIDR)

Read only

Reset Value: xx00 0000 (x0h)

Bits 7:6 =TP3-TP2

Token PID bits 3 & 2.

USB token PIDs are encoded in four bits. TP3-TP2

correspond to the variable token PID bits 3 & 2.

Note: PID bits 1 & 0 have a fixed value of 01.

When a CTR interrupt occurs (see register ISTR)

the software should read the TP3 and TP2 bits to

retrieve the PID name of the token received.

The USB standard defines TP bits as:

Bit 5:0 Reserved. Forced by hardware to 0.

INTERRUPT STATUS REGISTER (ISTR)

Read / Write

Reset Value: 0000 0000 (00h)

When an interrupt occurs these bits are set by

hardware. Software must read them to determine

the interrupt type and clear them after servicing.

Note: These bits cannot be set by software.

Bit 7 = Reserved. Forced by hardware to 0.

Bit 6 = DOVR

DMA over/underrun.

This bit is set by hardware if the ST7 processor

can’t answer a DMA request in time.

0: No over/underrun detected

1: Over/underrun detected

Bit 5 = CTR

Correct Transfer. This bit is set by

hardware when a correct transfer operation is

performed. The type of transfer can be determined

by looking at bits TP3-TP2 in register PIDR. The

Endpoint on which the transfer was made is

identified by bits EP1-EP0 in register IDR.

0: No Correct Transfer detected

1: Correct Transfer detected

Note:A transfer where the device sent a NAK or STALL

handshake is considered not correct (the host only

sends ACK handshakes). A transfer is considered

correct if there are no errors in the PID and CRC

fields, if the DATA0/DATA1 PID is sent as expect-

ed, if there were no data overruns, bit stuffing or

framing errors.

Bit 4 = ERR

Error.

This bit is set by hardware whenever one of the

errors listed below has occurred:

0: No error detected

1: Timeout, CRC, bit stuffing or nonstandard

framing error detected

Bit 3 = IOVR

Interrupt overrun.

This bit is set when hardware tries to set ERR,

ESUSP or SOF before they have been cleared by

software.

0: No overrun detected

1: Overrun detected

Bit 2 = ESUSP

End suspend mode.

This bit is set by hardware when, during suspend

mode, activity is detected that wakes the USB

interface up from suspend mode.

This interrupt is serviced by a specific vector.

0: No End Suspend detected

1: End Suspend detected

Bit 1 = RESET

USB reset.

This bit is set by hardware when the USB reset

sequence is detected on the bus.

0: No USB reset signal detected

1: USB reset signal detected

Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB,

EP2RA and EP2RB registers are reset by a USB

reset.

TP3

TP2

0000

TP3

TP2

PID Name

OUT

SETUP

DOVR

CTR

ERR

IOVR

ESUSP

RESET

SOF

ST72734 数据表(PDF) 81 Page - STMicroelectronics

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