ST72734 datasheet(20/144 Pages) STMICROELECTRONICS

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3.2 RESET

The Reset procedure is used to provide an orderly

software start-up or to quit low power modes.

Five conditions generate a reset:

LVD,

watchdog,

external pulse at the RESET pin,

illegal address,

illegal opcode.

A reset causes the reset vector to be fetched from

addresses FFFEh and FFFFh in order to be loaded

into the PC and with program execution starting

from this point.

An internal circuitry provides a 4096 CPU clock

cycle delay from the time that the oscillator

becomes active.

3.2.1 LVD and Watchdog Reset

The Low Voltage Detector (LVD) generates a reset

when VDD is below VTRH when VDD is rising or VTRL

when VDD is falling (refer to Figure 11). This circuitry

is active only when VDD is above VTRM.

During LVD Reset, the RESET pin is held low, thus

permitting the MCU to reset other devices.

When a watchdog reset occurs, the RESET pin is

pulled low permitting the MCU to reset other

devices as when Power on/off (Figure 10).

3.2.2 External Reset

The external reset is an active low input signal

applied to the RESET pin of the MCU.

As shown in Figure 12, the RESET signal must

remain low for 1000ns.

An internal Schmitt trigger at the RESET pin is

provided to improve noise immunity.

3.2.3 Illegal Address Detection

An opcode fetch from an illegal address (refer to

Figure 3) generates an illegal address reset.

Program

execution

those

addresses

forbidden (especially to protect page 0 registers

against spurious accesses).

3.2.4 Illegal Opcode Detection

Illegal instructions corresponding to no valid

opcode

generate

reset.

Refer

ST7

Programming Manual.

Table 5. List of sections affected by RESET and WAIT (Refer to 3.6 for Wait Mode)

Section

RESET

WAIT

Fast bit of the miscellaneous register set to one (24 MHz as external clock)

Timer Prescaler reset to zero

Timer Counter set to FFFCh

All Timer enable bits set to 0 (disabled)

Data Direction Registers set to 0 (as Inputs)

Set Stack Pointer to 01FFh

Force Internal Address Bus to restart vector FFFEh, FFFFh

Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)

Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)

Reset WAIT latch

Disable Oscillator (for 4096 cycles)

Set Timer Clock to 0

Watchdog counter reset

Watchdog register reset

Port data registers reset

Other on-chip peripherals: registers reset

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