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ST72734 数据表(PDF) 69 Page - STMicroelectronics

部件名 ST72734
功能描述  8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
PDF  144 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST72734 数据表(HTML) 69 Page - STMicroelectronics

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SYNC PROCESSOR (SYNC) (Cont’d)
MUX CONTROL REGISTER (MCR)
Read/Write
Reset Value: 0010 0000 (20h)
Bit 7:6 = BP1, BP0
Back Porch Pulse control
Bit 5 = FBSEL
VSYNCO/HSYNCO or VFBACK/
HFBACK analysis
0: HFBACK & VFBACK
1: HSYNCO & VSYNCO
Bit 4 = SCI0
HSYNCI/CSYNCI selection
0: HSYNCI
1: CSYNCI
Bit 3:2 = HS1, HS0
Horizontal Signal selection
These bits allow inversion of the HSYNCI/CSYNCI
Note: In case of composite sync, if HSYNCO blanking is
enabled (HINH=0 in the ENR register), HS1 must =
1 (CLAMPOUT after HSYNCO rising edge not al-
lowed).
Bit 1 = VOP
Vertical Polarity control
The VOP bit inverts the VSYNCO Sync signal.
0: No polarity inversion (VSYNC0 <- VSYNCI)
1: Inversion enabled (VSYNC0 <- VSYNCI)
Note: If at each vertical input capture the VPOL bit is cop-
ied by software on the VOP bit, the VSYNCO signal
will have a constant positive polarity.
Note: The internally extracted VSYNCO has ALWAYS
negative polarity.
Bit 0 = Reserved. Must always be cleared.
70
BP1
BP0
FBSEL SCI0
HS1
HS0
VOP
-
BP1
BP0
Back Porch pulse width
0
0
No Back Porch, Moire output selected
01
167ns Back Porch ± 10 ns
1
0
333ns Back Porch ± 10 ns
1
1
666ns Back Porch ± 10 ns
HS1
HS0
HSYNCI Selection Mode
00
CLAMPOUT after HSYNCO rising edge
HSYNC0 <- (HSYNCI, CSYNCI)
01
CLAMPOUT after HSYNCO rising edge
HSYNC0 <- (HSYNCI, CSYNCI)
10
CLAMPOUT after HSYNCO falling edge
HSYNC0 <- (HSYNCI, CSYNCI)
11
CLAMPOUT after HSYNCO falling edge
HSYNC0 <- (HSYNCI,CSYNCI)



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