ST72734 datasheet(28/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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I/O PORTS (Cont’d)

Table 7. I/O Pin Functions

4.1.2 Common Functional Description

Each port pin of the I/O Ports can be individually

configured under software control as either input

or output.

Each bit of a Data Direction Register (DDR)

corresponds to an I/O pin of the associated port.

This corresponding bit must be set to configure its

associated pin as output and must be cleared to

configure its associated pin as input (Table 7, “. I/O

Pin Functions,” on page 28). The Data Direction

Registers can be read and written.

The typical I/O circuit is shown on Figure 15. Any

write to an I/O port updates the port data register

even if it is configured as input. Any read of an I/O

port returns either the data latched in the port data

the I/O pins (pins configured as input).

Remark: when an I/O pin does not exist inside an

I/O port, the returned value is a logic one (pin

configured as input).

At reset, all DDR registers are cleared, which

configures all port’s I/Os as inputs with or without

pull-ups (see Table 8 to Table 12 I/O Ports

initialized at reset.

4.1.2.1 Input mode

When DDR=0, the corresponding I/O is configured

in Input mode.

In this case, the output buffer is switched off, the

state of the I/O is readable through the Data

from the CMOS Schmitt Trigger output and not

from the Data Register output.

4.1.2.2 Output mode

When DDR=1, the corresponding I/O is configured

in Output mode.

In this case, the output buffer is activated

according to the Data Register’s content.

A read operation is directly performed from the

Data Register output.

4.1.2.3 Analog input

Each I/O can be used as analog input by adding an

analog switch driven by the ADC.

The I/O must be configured in Input before using it

as analog input.

The CMOS Schmitt trigger is OFF and the analog

value directly input through an analog switch to the

Analog to Digital Converter, when the analog

channel is selected by the ADC.

4.1.2.4 Alternate mode

A signal coming from a on-chip peripheral can be

output on the I/O.

In this case, the I/O is automatically configured in

output mode.

This must be controlled directly by the peripheral

with a signal coming from the peripheral which

enables the alternate signal to be output.

A signal coming from an I/O can be input in a on-

chip peripheral.

Before using an I/O as Alternate Input, it must be

configured in Input mode (DDR=0). So both

Alternate

Input

configuration

and

I/O

Input

configuration are the same (with or without pull-

up). The signal to be input in the peripheral is taken

after the CMOS Schmitt trigger or TTL Schmitt

trigger for SYNC.

The I/O state is readable as in Input mode by

addressing the corresponding I/O Data Register.

DDR

MODE

Input

Output

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