ST72734 datasheet(82/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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USB INTERFACE (Cont’d)

Bit 0 = SOF

Start of frame.

This bit is set by hardware when a low-speed SOF

indication (keep-alive strobe) is seen on the USB

bus.

0: No SOF signal detected

1: SOF signal detected

Note: To avoid spurious clearing of some bits, it is recom-

mended to clear them using a load instruction

where all bits which must not be altered are set, and

all bits to be cleared are reset. Avoid read-modify-

write instructions like AND , XOR..

INTERRUPT MASK REGISTER (IMR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = Reserved. Forced by hardware to 0.

Bits 6:0 = These bits are mask bits for all interrupt

condition bits included in the ISTR. Whenever one

of the IMR bits is set, if the corresponding ISTR bit

is set, and the I bit in the CC register is cleared, an

interrupt request is generated. For an explanation

of each bit, please refer to the corresponding bit

description in ISTR.

CONTROL REGISTER (CTLR)

Read / Write

Reset Value: 0000 0110 (06h)

Bits 7:4 = Reserved. Forced by hardware to 0.

Bit 3 = RESUME

Resume.

This bit is set by software to wake-up the Host

when the ST7 is in suspend mode.

0: Resume signal not forced

1: Resume signal forced on the USB bus.

Software should clear this bit after the appropriate

delay.

Bit 2 = PDWN

Power down.

This bit is set by software to turn off the 3.3V on-

chip voltage regulator that supplies the external

pull-up resistor and the transceiver.

0: Voltage regulator on

1: Voltage regulator off

Note: After turning on the voltage regulator, software

should allow at least 3 µs for stabilisation of the

power supply before using the USB interface.

Bit 1 = SUSP

Suspend mode.

This bit is set by software to enter Suspend mode.

0: Suspend mode inactive

1: Suspend mode active

When the hardware detects USB activity, it resets

this bit (it can also be reset by software).

Bit 0 = FRES

Force reset.

This bit is set by software to force a reset of the

USB interface, just as if a RESET sequence came

from the USB.

0: Reset not forced

1: USB interface reset forced.

The USB is held in RESET state until software

clears this bit, at which point a “USB-RESET”

interrupt will be generated if enabled.

DEVICE ADDRESS REGISTER (DADDR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = Reserved. Forced by hardware to 0.

Bits 6:0 = ADD[6:0]

Device address, 7 bits.

Software must write into this register the address

sent by the host during enumeration.

Note: This register is also reset when a USB reset is re-

ceived from the USB bus or forced through bit

FRES in the CTLR register.

DOV

CTR

ERR

IOVR

ESU

SPM

RES

ETM

SOF

RESUME

PDWN

SUSP

FRES

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

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