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ST72734 数据表(PDF) 73 Page - STMicroelectronics

部件名 ST72734
功能描述  8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
PDF  144 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST72734 数据表(HTML) 73 Page - STMicroelectronics

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SYNC PROCESSOR (SYNC) (Cont’d)
ENABLE REGISTER (ENR)
Read/Write
Reset Value: 1100 0011 (C3h)
Bit 7 = SYNOP
HSYNCO, VSYNCO outputs
enable
0: Enabled
1: Disabled
Bit 6 = CLMPEN
Clamping or Moire output ena-
ble
0: Clamping or Moire output (function of BP0,
BP1) enabled
1: Clamping or Moire output disabled
Bit 5 = BLKEN
Blanking Output
0: Disabled
1: Enabled
Bit 4 = HVGEN
Sync Generation function
0: Analyzer/Corrector Mode
1: Generation of HSYNCO and VSYNCO free-
running frequencies
Bit 3 = 2FHEN
VSYNCO Extension
VSYNCO is forced high when detecting pre- and
post-equalization pulses. It is valid when the sync
generator and analyzer are disabled (HVGEN = 0,
HACQ = 0, VACQ = 0). Refer to the procedure in
Section 4.4.9 Corrector Mode.
0: Disabled
1: Enabled
Bit 2 = HINH
HSYNCO Blanking
HSYNCO
is
blanked
during
the
extracted
VSYNCO pulse.
0: Enabled
1: Disabled
Bit 1 = HSIN1 (read only)
Returns the HSYNCI1 pin level
Bit 0 = VSIN1 (read only)
Returns the VSYNCI1 pin level
Table 20. Summary of the Main Sync Processor Modes
70
SYNOP CLMPEN BLKEN HVGEN 2FHEN HINH HSIN1 VSIN1
Sync Processor Mode
SYNOP
HVSEL
HVGEN
HACQ
VACQ
DSUB Selected as Inputs
(HSYNCI1/VSYNCI1)
---
1
---
---
---
BNC Selected as Inputs
(HSYNCI2/VSYNCI2)
---
0
---
---
---
Don’t drive the monitor
with any Sync signals
1
---
---
---
---
Generate Sync Signals
to drive the Monitor hardware
0
---
1
0
0
Use the Sync Processor
to drive the monitor hardware
by incoming Sync signals
0
---
0
---
---
Analyse the number of Scan Lines
during one vertical frame
---
--
0
---
1
Analyse the HSYNC delay
between two pulses
---
---
0
1
---



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