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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST72734 数据表(PDF) 90 Page - STMicroelectronics |
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ST72734 数据表(HTML) 90 Page - STMicroelectronics |
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90 / 144 page  ST72774/ST727754/ST72734 90/144 I²C SINGLE MASTER BUS INTERFACE (Cont’d) Figure 54. Transfer Sequencing Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV2: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV4: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. Figure 55. Event Flags and Interrupt Generation Master receiver: Master transmitter: S Address A Data1 A Data2 A ..... DataN NA P EV1 EV2 EV3 EV3 EV3 S Address A Data1 A Data2 A ..... DataN A P EV1 EV2 EV4 EV4 EV4 EV4 BTF SB AF EVF INTERRUPT ITE * * EVF can also be set by EV2 or an error from the SR2 register. * |
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