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ST72734 数据表(PDF) 102 Page - STMicroelectronics |
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ST72734 数据表(HTML) 102 Page - STMicroelectronics |
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102 / 144 page ![]() ST72774/ST727754/ST72734 102/144 DDC INTERFACE (Cont’d) DDC2B Mode: The DDC1/2B Interface enters DDC2B mode either from the transition state or from the initial state if software sets the HWPE bit while P&D only or FPDI-2 mode is selected. Once in DDC2B mode, the Interface always acts as a slave following the protocol described in Figure 62. The DDC1/2B Interface continuously monitors the SDA and SCL lines for a START condition and will not respond (no acknowledge) until one is found. A STOP condition at the end of a Read command (after a NACK) forces the stand-by state. A STOP condition at the end of a Write command triggers the internal DMA write cycle. The Interface samples the SDA line on the rising edge of SCL and outputs data on the falling edge of SCL. In any case SDA can only change when SCL is low. Figure 62. DDC2B protocol (example) SDA SCL Start Ack A0h Device Slave 00h Data Address Ack Start A1h Data1 Ack DataN Nack Stop Stop Address Device Slave Address 128 / 256 bytes EDID Legend: Italics = data / control signal from display Ack Bold = data / control signal from host |
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