LM4560 datasheet(25/54 Pages) NSC

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3.0 Register Description (Continued)

Note: Controlled by PCMIN_SEL in Reg48h, either of Primary CODEC PC-

MIN slot or Secondary CODEC PCMIN slot will come into 3-level PC-

MIN_A buffer. And if PCMIN_B Mixing bit is enabled, the other slot will

come into 1-level PCMIN_B buffer and will be mixed into Main Mixer.

Bit 16 64-Channel Mode

0 Legacy Mode

1 64-Channel Mode

Bit 15–10 is used for global control.

Bit 15 (EDROP_IE) is INT enable bit for current envelope

dropping to −63.984375 dB.

0: disable

1: enable

Bit 14 (ETOG_IE) is INT enable bit for envelope buffer tog-

gling.

0: disable

1: enable

Bit 13 (MIDLP_IE) is INT enable bit for middle of loop.

0: disable

1: enable

Bit 12 (ENDLP_IE) is INT enable bit for end of loop.

0: disable

1: enable

Bit 11 (UNDERUN_IE) is INT enable bit for playback under-

run.

0: disable

1: enable

When playback FIFO is empty, if this bit is set as ‘1’, an IRQ

will be issued.

Bit 10 (OVERUN_IE) is INT enable bit for recording overrun.

0: disable

1: enable

When recording FIFO is full, if this bit is set as ‘1’, an IRQ will

be issued.

Bit 9 (Pause/Resume) is Pause/Resume command bit.

Read: 0: Engine hasn’t been paused yet.

1: Engine has been paused already.

Write: 0: Resume Engine.

1: Pause Engine.

When host writes ‘1’, this bit may not show ‘1’ immediately.

Engine will try to get paused as soon as possible. After en-

gine has been paused already, this bit will be set to ‘1’. Once

host writes ‘0’, this bit will be reset to ‘0’ immediately and en-

gine will work normally.

Bit 8 (RST_Stimer) is used to reset playback sample timer

counter.

When read, return 0;

write 1 will reset STimer.

Bits 5–0 (CIR) is the channel index which is used to select a

channel for access. 00h selects channel 0, 1Fh selects

channel 31, 3Fh selects channel 63.

All other bits are reserved.

3.2.9.10 AINTEN_A (Bank A Address Engine Interrupt

Enable)

Address: AudioBase + A4h

Size:

32 bits

Type:

Read/Write

Default:

00000000h

This register will control address engine interrupt for each

channel of Bank A. Bit n is for channel n.

0: disable address engine interrupt for channel n

1: enable address engine interrupt for channel n

3.4.9.11 MUSICVOL & WAVEVOL (Global Music Volume

& Global Wave Volume)

Address: AudioBase + A8h

Size:

32 bits

Type:

Read/Write

Default:

00008080h

MUSICVOL (Bit 3–16) is global music left/right volume in for-

mat of 6.2

Bit 23–16 music left volume

0 0 dB (no attenuation)

FFh −63.75 dB (mute)

Bit 31–24 music right volume

0 0dB (no attenuation)

FFh −63.75 dB (mute)

WAVEVOL (Bit 15–0) is global wave left/right volume in for-

mat of 6.2

Bit 7–0 wave left volume

0 0 dB (no attenuation)

80h –32 dB (default)

FFh −63.75 dB (mute)

Bit 15–8 wave right volume

0 0 dB (no attenuation)

80h –32 dB (default)

FFh − 63.75 dB (mute)

3.4.9.12 SBDELTA/DELTA_R (Sample Change Step for

Legacy Playback & Recording)

Address: AudioBase + ACh

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Bit15–0 (SBDELTA/SBDELTA_R): SBDELTA: Fs/F48k in

4.12 format.

SBDELTA_R: F48k/Fs in 4.12 format.

Bit 31–16: Reserved.

3.4.9.13 MISCINT (Miscellaneous Int & Status)

Address: AudioBase + B0h

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Bit[7:0] (read only) are interrupt request bits. All of these six

bits form signal AUDIO_INT.

AUDIO_INT = PB_UNDERUN_IRQ | REC_OVERUN_IRQ |

SB_IRQ | MPU401_IRQ | OPL3_IRQ | ADDRESS_IRQ | EN-

VELOPE_IRQ | ST_IRQ | ACGPIO_IRQ

Bit 0 (PB_UNDERUN_IRQ) is playback FIFO underrun IRQ

bit. Active high.

Bit[0] = UNDERUN_IE & Bit[8].

Bit 1 (REC_OVERUN_IRQ) is recording overrun IRQ bit. Ac-

tive high.

Bit[1] = OVERUN_IE & Bit[9].

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