LM4560 datasheet(24/54 Pages) NSC

24 / 54 page

3.0 Register Description (Continued)

A ‘1’ written to bit n will reset this bit.

3.4.9.8 EINT (Envelope Engine Interrupt Eegister) (for

Bank A only)

Address: AudioBase + 9Ch

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Any bits toggled from ‘0’ to ‘1’ will result in a IRQ.

Reading from this I/O port will return the envelope INT status

of 32 channels of Bank A. Bit n is for channel n.

0: No INT

1: INT

This bit will be set in 2 cases:

When envelope buffer toggled, and ETOG_IE ( envelope

toggle INT enable bit in Global Control register ) =1.

When Ec (current envelope)

≤ FFFh (−63.984375 dB), and

EDROP_IE (envelope dropping to −63.984375 dB INT en-

able bit in Global Control register) =1.

Writing ‘1’ to bit n of this register will reset this bit.

0: Ignore.

A ‘0’ written to bit n will not change the status of this bit.

1: reset

A ‘1’ written to bit n will reset this bit.

3.4.9.9 GC & CIR (Global Control & Channel Index)

Address: AudioBase + A0h

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Bits 31–30 are used to control Legacy Recording channel

when record to mono sample.

00: left

01: right

10: (left+right+1)/2

11: reserved.

Bits 29–28 are IO 0008-read handling control bits.

00: never assert StatusRDY

01: StatusRDY = DMATCReached

10: StatusRDY = DMATCReached | LegacyDRQ

11: in this case, handshaking with StatusWR and manipula-

tion of return byte should been done.

StatusRDY keep ‘0’ when initialization.

If(StatusWR == 1) {

StatusRDY = 1;

if(DMAChannel==0) {

ReturnByte[7:0]=

{InputByte[7:5], DMAR8[4], InputByte[3:1], DMAR8[0]};

}

else {

ReturnByte[7:0] =

{InputByte[7:6], DMAR8[5], InputByte[4],

InputByte[3:2], DMAR8[1], InputByte[0]};

}

if(DMASNOOPCS_==0 & ADR[7:0]=8& Data_rdy_ == 0 &

StatusRDY==1)

StatusRDY = 0;

Bit 27 Test_loopback: This bit is used for wave engine loop-

back testing.

0: normal

1: force recording engine get new data from playback FIFO

instead of aclink.

Bit 26 Debugging Mode

0: Normal

1: Chip is in Debugging Mode.

In Debugging Mode, 20 pins (including 8 pins of GPIO, 1 pin

of SPDIF, 6 pins of I2S and 5 NC pins) are used as output to

monitor 40 internal important signals.

Detail in Appendix B.

Bit 25–24 EXPROM Map Mode

00: 000h–1FFh of EXPROM is mapped to AudioMemBase

800h–FFFh low 16 bits;

800h–9FFh of EXPROM is mapped to AudioMemBase

800h–FFFh high 16 bits;

01: 200h–3FFh of EXPROM is mapped to AudioMemBase

800h–FFFh low 16 bits;

A00h–BFFh of EXPROM is mapped to AudioMemBase

800h–FFFh high 16 bits;

10: 400h–5FFh of EXPROM is mapped to AudioMemBase

800h–FFFh low 16 bits;

C00h–DFFh of EXPROM is mapped to AudioMemBase

800h–FFFh high 16 bits;

11: 600h–7FFh of EXPROM is mapped to AudioMemBase

800h–FFFh low 16 bits;

E00h–FFFh of EXPROM is mapped to AudioMemBase

800h–FFFh high 16 bits.

Bit 23 EXPROM Dump Mode Enable

0: Disable

1: Enable

If enabled, EXPROM(4096x12bit) is mapped to AudioMem-

Base according to bit[25:24], i.e. the content of EXPROM

can be read out through AudioMem Read cycle.

Bit 22–21 Test mode bits

00: normal mode (chip works normally in this mode)

01: test mode 1

10: test mode 2

11: test mode 3

The detail descriptions on test mode 1, 2, and 3 are given in

Appendix B.

Bit 20 Main Mixer Output Control

0 Main Mixer L/R → PCM L/R Output FIFO

1 Main Mixer L/R → MMC L/R Output Buffer

Bit 19 S/PDIF Out Control

0 S/PDIF L/R Output Buffer → S/PDIF L/R transmitter

1 PCM L/R Output FIFO → S/PDIF L/R transmitter

Bit 18 I2S Out Control

0 I2S L/R Output Buffer → I2S transmitter

1 SURR L/R Output FIFO → I2S transmitter

Bit 17 PCMIN_B Mixing Enable/Disable

0 PCMIN_B Mixing Disable

1 PCMIN_B Mixing Enable

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