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LM4560 数据表(PDF) 52 Page - National Semiconductor (TI) |
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LM4560 数据表(HTML) 52 Page - National Semiconductor (TI) |
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52 / 54 page ![]() Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V DD) −0.5V to 4.0V Input Voltage (V I) −0.5V to 5.5V +0.5V Output Voltage (V O) −0.5V to V DD +0.5V Storage Temperature (T STG) −65˚C to +165˚C Power Dissipation (P D)1W Lead Temperature (T L) (Soldering, 10 seconds) +200˚C 7.2 CAPACITANCE T A = 0˚C to 70˚C, Vdd = 3.3V ±5%,VSS = 0V (Note 2) Symbol Parameter Conditions Min Typ Max Units C IN Input Pin Capacitance 10 pF C ICLK Clock Input Capacitance 12 pF C IO I/O Pin Capacitance f = 1 MHz 10 pF C O Output Pin Capacitance f = 1 MHz 10 pF Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Capacitance limits are guaranteed by simulation but are not tested. 7.3 ELECTRICAL CHARACTERISTICS T A = 0˚C to 70˚C, Vdd = 3.3V ±5%,VSS =0V Symbol Parameter Conditions Min Typ Max Units I CC V DD Average Supply Current V DD = 3.3V, VIL = 0.5V, V IH = 2.4V, No Load 20 35 50 mA V IH Input High Voltage 1.65 5.5 V V IL Input Low Voltage −0.5 1.0 V CORE (3.3V Only) CV cc Core Supply Voltage 3.2 3.4 V I/O - 3.3V Signalling Environment V ih Input High Voltage 1.65 V dd V V il Input Low Voltage 1.0 V V oh Output High Voltage 2.97 V V ol Output Low Voltage 0.33 V Gameport I/O DC Characteristic (for pull up resistor values of 2.5k to 10k Ω) Vtranlh For Schmitt trigger I/O, Input voltage at trigger point (output is V cc/2 When input goes from low to high 2.1 V Vtranhl For Schmitt trigger I/O, Input voltage at trigger point (output is V cc/2 When input goes from high to low 1.3 V 7.4.1 Timing Table T A = 0˚C to 70˚C, Vdd = 3.3V ±5%,VSS =0V Symbol Parameter Min Max Units PCI Clock Tcyc CLK Cycle Time 30 ns Thigh CLK High Time 14 16 ns Tlow CLK Low Time 14 16 ns Tskew CLK Skew −2 2 ns AC’97 Clock Tcyc ACCLK Cycle Time 72 ns Thigh ACCLK High Time 36 45 ns Tlow ACCLK Low Time 36 45 ns www.national.com 52 |
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