LM4560 datasheet(14/54 Pages) NSC

14 / 54 page

3.0 Register Description (Continued)

3.4.1.10 DMAR10 (Legacy DMA Single Channel Mask

Port)

Address: AudioBase + 0Ah or 000Ah

Size:

8 bits

Type:

Write Only

Default:

00h

Write: channel mask register for implemented legacy 8237-A

DMA channel.

Writing to this register will affect the legacy DMA operation of

the LM4560, implementation of this register maintains the

Master’s responsibility to update the legacy channel mask

bit, DMAR15.0 with address (DMASlaveBase + Fh) when a

I/O write to 000Ah occurred on PCI Bus. When snooping a

legacy 8237-A register operation is enabled, any I/O write to

000Ah should be snooped to DMAR15.0.

3.4.1.11 DMAR11 (Legacy DMA Channel Operation

Mode Register)

Address: DMASlaveBase + 0Bh or AudioBase + 0Bh or

000Bh

Size:

8 bits

Type:

Read/Write

Default:

00h

Write: channel mode register for implemented legacy 8237-A

DMA channel.

Writing to this register will affect the legacy DMA operation of

the LM4560, implementation of this register maintains the

which has DDMA Master, it is the DMA Master’s responsibil-

ity to update this register when an I/O write to 000Bh oc-

curred on PCI Bus. When snooping legacy 8237-A register

operation is enabled, any I/O write to 000Bh should be

snooped to this register if the channel number matches the

snooping legacy DMA channel number.

Read : This register can only be read out through AudioBase

+ 0Bh port.

3.4.1.12 DMAR12 (Legacy DMA Controller First_Last

Flag Clear Port)

Address: AudioBase + 0Ch or 00Ch

Size:

0 bits

Type:

Write Only

Write: first_last flag clear register for implemented legacy

8237-A DMA channel.

Writing to this register will clear the flag signal First_Last.

Implementation of this register maintains the register com-

patibility with legacy 8237-A DMA controller for system with-

out DDMA Master. For system which has DDMA Master, it is

the DMA Master’s responsibility to implement this flag. When

snooping legacy 8237-A register operation is enabled, any

I/O write to 000Ch should clear First_Last flag.

3.4.1.13 DMAR13 (Legacy DMA Controller Master Clear

Port)

Address: DMASlaveBase + 0Dh or AudioBase + 0Dh or

000Dh

Size:

0 bits

Type:

Write Only

Write : master clear register for implemented legacy 8237-A

DMA channel.

Writing to this register has the effect of hardware reset to the

implemented legacy 8237-A DMA channel. Implementation

of this register maintains the register compatibility with

legacy 8237-A DMA controller for system with or without

DDMA Master. For system which has DDMA Master, it is the

DMA Master’s responsibility to write to this register when a

write to legacy 8237-A master clear register (I/O write to

000Dh) is on the PCI Bus. When snooping legacy 8237-A

clear several legacy flags such as First_Last flag.

3.4.1.14 DMAR14 (Legacy DMA Controller Clear Mask

Port)

Address: AudioBase + 0Eh or 000Eh

Size:

0 bits

Type:

Write Only

Write: multi-channel mask clear port for implemented legacy

8237-A DMA channel.

Writing to this register will affect the legacy DMA operation.

Implementation of this register maintains the register com-

patibility with legacy 8237-A DMA multi-channel clear mask

Master’s responsibility to update the legacy channel mask bit

DMAR15.0 with address (DMASlaveBase + Fh) when a I/O

write to 000Eh occurred on PCI Bus. When snooping legacy

8237-A register operation is enabled, any I/O write to 000Eh

will reset DMAR15.0 to 0.

3.4.1.15 DMAR15 (Legacy DMA Controller

Multi-Channel Mask Register)

Address: DMASlaveBase + 0Fh or AudioBase + 0Fh or

000Fh

Size:

1 bit

Type:

Write Only

Default:

Write: multi-channel mask register for implemented legacy

8237-A DMA channel.

Implementation of this register maintains the register com-

patibility with legacy 8237-A DMA controller for system with

or without DDMA Master. For system which has DDMA Mas-

ter, it is the DMA Master’s responsibility to write DMAR15

when a write to legacy 8237-A multi-channel mask register

(I/O write to 000Fh) is on the PCI Bus. When snooping

legacy 8237-A register operation is enabled, any I/O write to

000Fh should update the mask flag for the implemented

legacy 8237-A DMA channel.

3.4.2 Legacy Sound Blaster/Adlib Register:

These 16-byte registers can be accessed on Audio Base (I/O

or MEM), SB Base, or ADLIB Base.

3.4.2.1 SBR0 (Legacy FmMusic Bank 0 Register Index /

Legacy FmMusic Status)

Address: AudioBase + 10h or SBBase + 0h or SBBase +

08h or ADLIBBase + 0h

Size:

8 bits

Type:

Read/Write

Default:

00h

Write

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