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LM4560 数据表(PDF) 30 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 LM4560
功能描述  Advanced PCI Audio Accelerator
PDF  54 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

LM4560 数据表(HTML) 30 Page - National Semiconductor (TI)

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3.0 Register Description (Continued)
when Bit[31:30] = 1x (REC or REC_PB)
00: left,
01: right
10: (left+right+1)/2
11: reserved.
Bit[23] SRC Enable
0 disable
1 enable
Bit[22] FM and AM Enable
0 disable
1 enable
Bit[21] PAN Enable
0 disable
1 enable
Bit[20] Channel Volume Enable
0 disable
1 enable
Bit[19] Global Volume Enable
0 disable
1 enable
Bit[18:16] reserved
Bit[15:14] (FMC) FM modulation control bits.
00: FMA = (FMS * SIN) >> 3
01: FMA = (FMS * SIN) >> 2
10: FMA = (FMS * SIN) >> 1
11: FMA = (FMS * SIN) >> 0
Bit[13:7] (RVOL) Reverb Send Linear Volume
format: 1.6, 7Fh stands for 2x gain, 40h stands for no gain no
attenuation, 00h stands for mute.
Bit[6:0] (CVOL) Chorus Send Linear Volume
format: 1.6, 7Fh stands for 2x gain, 40h stands for no gain no
attenuation, 00h stands for mute.
3.4.9.29 F0h_A (Bank A GVSEL & PAN & VOL & CTRL
& Ec) (for Bank A only)
This register can be accessed in index mode or direct ac-
cess mode.
Address:
AudioBase + F0h (index mode) || Audio MEM
Base + 810h + 20h*CIR (direct access mode,
CIR: channel index) (CIR<32)
Size:
32 bits
Type:
Read/Write
Default:
XXXXXXXXh
Description: GVSEL — Global Volume Select (1 bit)
PAN — Positioning Attenuation (7 bits)
VOL — Volume Attenuation (8 bits)
CTRL — Control (4 bits)
Ec — Curent Envelope (12 bit)
Bit 31 (GVSEL) is global volume select bit.
0: select MUSICVOL
1: select WAVEVOL
Bits 30–24 (PAN) is Positioning attenuation control.
Bit 30 selects attenuated channel.
0: left,
1: right.
Bits 29–24 is the attenuation value in format of 4.2. 3Fh
stand for mute.
Bits 23–16 (VOL) is channel volume attenuation in format of
5.3. 00h stands for 0 dB attenuation, FFh stands for mute.
Bits 15–12 are control bits.
Bit 15 selects 8/16 bit sample data
0: 8-bit data
1: 16-bit data
Bit 14 selects mono/stereo sample data
0: mono
1: stereo
Bit 13 selects unsigned/signed sample data
0: unsigned
1: signed
Bit 12 is loop mode enable bit.
0: disable
1: enable
Bit 11–0 (Ec) is current envelope in format of 6.6 (Six bits in-
teger and six bits fraction). 00h stands for 0 dB, FFh stands
for −63.984375 dB.
3.4.9.30 F0h_B (Bank B GVSEL & PAN & VOL & CTRL
& Bank A LFO_INIT)
This register can be accessed in index mode or direct ac-
cess mode.
Address:
AudioBase + F0h (index mode) || Audio MEM
Base + 810h + 20h*CIR (direct access mode,
CIR: channel index) (CIR<32)
Size:
32 bits
Type:
Read/Write
Default:
XXXXXXXXh
Description: GVSEL — Global Volume Select (1 bit)
PAN — Positioning Attenuation (7 bits)
VOL — Volume Attenuation (12 bits)
CTRL — Control (4 bits)
LFO_INIT — Bank A per channel LFO counter
initial and reload value(8 bit)
Bit 31 (GVSEL) is global volume select bit.
0: select MUSICVOL
1: select WAVEVOL
Bits 30–24 (PAN) is Positioning attenuation control.
Bit 30 selects attenuated channel.
0: left,
1: right.
Bits 29–24 is the attenuation value in format of 4.2. 3Fh
stand for mute.
Bits 23–16 (LFO_INIT) is Bank A per channel LFO counter
initial and reload value.
Note: Any time when host write to RegECh[26:16] (LFO_CT), LFO_INIT
should be written with the same value.
Bits 15–12 are control bits.
Bit 15 selects 8/16 bit sample data
0: 8-bit data
1: 16-bit data
Bit 14 selects mono/stereo sample data
0: mono
1: stereo
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