LM4560 datasheet(19/54 Pages) NSC

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3.0 Register Description (Continued)

Default:

00000000h

Write

Bit 7..0

index of the AC-97 mixer register to

be written;

Bit7=0for Primary CODEC;

Bit7=1for Secondary CODEC.

Bit 14..7

reserved

Bit 15

do nothing

write AC-97 mixer register (indexed

by bit 7..0) with bit 31..16;

Bit 31..16

data to be written into AC-97 mixer

Read

Bit 6..0

index of the AC-97 mixer register to

be written;

Bit 14..7

reserved

Bit 15

ready to write AC-97 mixer register

busy writing AC-97 mixer (indexed

by Bit 7..0);

Bit 31..16

data to be written into AC-97 mixer

3.4.5.2 ACRD (AC-97 Mixer Read Register)

Address: AudioBase + 44h

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Write

Bit 7..0

index of the AC-97 mixer register to

be read;

Bit 7=0 for Primary CODEC;

Bit 7=1 for Secondary CODEC.

Bit 14..7

reserved

Bit 15

do nothing

read AC-97 mixer register (indexed

by bit 7..0) with bit 31..16;

Bit 31..16

reserved

Read

Bit 6..0

index of the AC-97 mixer register to

be read;

Bit 14..7

reserved

Bit 15

bit 31..16 is valid data of the AC

mixer register (indexed by bit 7..0)

busy reading AC-97 mixer register

(indexed by Bit 7..0);

Bit 31..16

AC-97 mixer register contents.

3.4.5.3 SCTRL (Serial INTF Control Register)

Address: AudioBase + 48h

Size:

32 bits

Type:

Read/Write

Default:

00014000h

Bit 0 (WRST_CODEC) CODEC Warm Reset Command

0: Normal

1: Warm Reset CODEC

When write ‘1’ to this bit, pin ACSYNC should be driven to

high for at least 1µs.

Bit 1 (CRST_CODEC) CODEC Cold Reset Command

0: Normal

1: Cold Reset CODEC

When write ‘1’ to this bit, pin ACRST should be driven to low

for at least 1µs.

Bit 2 (MCLK_SEL) MCLK clock rate select for I2S Output

0: MCLK = 12.288M

1: MCLK = 6.144M

Bit 3 (PCMOUT_SEL) PCM Output Select (Primary/

Secondary)

0: PCM Output up to Primary CODEC request

1: PCM Output up to Secondary CODEC request

Bit 4 (DBLRATE_EN) CODEC Double Rate Enable

0: Disable

1: Enable

Bit 5 (SPDIF_EN) S/PDIF Output Function Enable

0: Disable

If disabled, the clocks of SPDIF transmitter should be shut

down.

1: Enable

Bit 6 (I2SOUT_EN) I2S Output Function Enable

0: Disable

If disabled, the clocks of I2S transmitter should be shut

down.

1: Enable

Bit 7 (I2SIN_EN) I2S Input Function Enable

0: Disable

If disabled, the clocks of I2S receiver should be shut down.

1: Enable

Bit 8 (PCMIN_SEL) PCMIN Slot Select

0: Primary CODEC PCMIN slot input to PCMIN_A buffer

1: Secondary CODEC PCMIN slot input to PCMIN_A buffer

Bit 9 (LINE1IN_SEL) LINE1IN Slot Select

0: Primary CODEC LINE1IN slot input to LINE1IN buffer

1: Secondary CODEC LINE1IN slot input to LINE1IN buffer

Bit 10 (MIC_SEL) MIC Slot Select

0: Primary CODEC MIC slot input to MIC buffer

1: Secondary CODEC MIC slot input to MIC buffer

Bit 11 (LINE2IN_SEL) LINE2IN Slot Select

0: Primary CODEC LINE2IN slot input to LINE2IN buffer

1: Secondary CODEC LINE2IN slot input to LINE2IN buffer

Bit 12 (HSETIN_SEL) HSETIN Slot Select

0: Primary CODEC HSETIN slot input to HSETIN buffer

1: Secondary CODEC HSETIN slot input to HSETIN buffer

Bit 13 (GPIOIN_SEL) GPIOIN Slot Select

0: Primary CODEC GPIOIN slot input to GPIOIN buffer

1: Secondary CODEC GPIOIN slot input to GPIOIN buffer

Bit 15–14 Secondary CODEC ID

Default: 01

Bit 16 (PCMOUT_EN) PCMOUT L/R Slot Enable, Default: 1

0: Disable

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