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LM4560 数据表(PDF) 53 Page - National Semiconductor (TI) |
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LM4560 数据表(HTML) 53 Page - National Semiconductor (TI) |
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53 / 54 page ![]() 7.4.1 Timing Table (Continued) T A = 0˚C to 70˚C, Vdd = 3.3V ±5%,VSS =0V Symbol Parameter Min Max Units PCI Reset Trst_low RST# low time after power stable 1 ms Trst_clk RST# low time after PCICLK stable 100 µs AC’97 Reset (Cold and Warm) Trst_low ACRST_low time 1 µs Trst2clk ACRST_ inactive to ACCCLK starts 162.8 ns Tsync_high ACSYNC high time 1 µs Tsync2clk ACSYNC_ inactive to ACCCLK starts 162.8 ns 7.4.2 PCI Signals PCI Inputs: AD31:0, CBE#3:0, FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, IDSEL#, PAR, GNT# PCI Outputs: AD31:0, CBE#3:0, FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, IDSEL#, PAR, REQ#, INTA# Point-to-Point Signals: REQ#, GNT# Symbol Parameter Condition Min Max Units Tval_bus CLK to PCI output Valid Delay_ bussed signals 211 ns Tval_ptp CLK to PCI output Valid Delay_ point to point signals 212 ns Ton PCI Output float to active 2 ns Toff PCI Output active to float 28 ns AD0:31 bus PCI Input set up time to CLK_ bussed signals 9ns Tsu GNT PCI Input set up time to CLK_GNT# 12 ns Tsu REQ PCI Input set up time to CLK_REQ# 12 ns Th PCI Input hold time from CLK 0 ns AC’97 Signals Tsetup Setup from edge of ACCLK 10 ns Thold Hold from edge of ACCLK 10 ns www.national.com 53 |
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