LM4560 datasheet(11/54 Pages) NSC

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3.0 Register Description (Continued)

IO Offset

+3h

+2h

+1h

+0h

B0h

MISCINT

B4h

START_B

B8h

STOP_B

BCh

CSPF_B

C0h

SBDMAL

SBDMAC

C4h

SCE2R

RSVD

SBDD

SBCTRL

C8H

STIMER

CCh

LFO_CTRL_B

LFO_CT_B

RSVD + I

2S_DELTA

D0h

ST_TARGET

D4h

RSVD

D8h

AINT_B

DCh

AINTEN_B

Bank A: Channel Register

ARAM_A (CIR<32)

E0h

CSO

FMS+ALPHA(11:8)

ALPHA(7:0)

E4h

CPTR + LBA

E8h

ESO

DELTA

ECh

LFO_CTRL

LFO_CT

FMC+RVOL[6:1]

RVOL[0]+CVOL

F0h

GVSEL + PAN

VOL

CTRL + Ec(11:8)

Ec(7:0)

F4h

EBUF1

F8h

EBUF2

FCh

RSVD

Bank B: Channel Register

ARAM_B (CIR>=32)

E0h

CSO

FMS+ALPHA(11:8)

ALPHA(7:0)

E4h

CPTR + LBA

E8h

ESO

DELTA

ECh

ATTRIBUTE

FMC+RVOL[6:1]

RVOL[0]+CVOL

ERAM_B (CIR>=32)

F0h

GVSEL + PAN

LFO_INIT(Bank A)

CTRL + VOL(11:8)

VOL(7:0)

F4h

RSVD

F8h

RSVD

FCh

RSVD

3.1.1.15 I/O Access Mode:

3.1.1.15.1 Audio I/O Base:

The Audio Processor requires a 256-byte PCI I/O space. The

base address (called the Audio I/O Base) resides in PCI

Configuration Register 10h.

All audio processor registers (00h–FFh) can be accessed by

host in an I/O cycle with address: Audio I/O Base+offset.

3.1.1.15.2 Legacy SB I/O Base:

If CFG_REG44h[0] is ‘0’, SB I/O Base is 220h; if

CFG_REG44h[0] is ‘1’, SB I/O Base is 240h.

There are 16 byte registers in SB I/O Base. Physically, those

registers are aliased to Audio Base Reg10h–1Fh.

3.1.1.15.3 Legacy ADLIB I/O Base:

If CFG_REG44h[2] is ‘0’, ADLIB I/O Base is 388h; if

CFG_REG44h[2] is ‘1’, ADLIB I/O Base is 38Ch.

There are 4 byte registers in ADLIB I/O Base. Physically,

those registers are alaised to Audio Base Reg10h–13h.

3.1.1.15.4 Legacy Gameport I/O Base:

If CFG_REG44h[4] is ‘0’, Gameport I/O Base is 200h; if

CFG_REG44h[4] is ‘1’, Gameport I/O Base is 208h.

There are 8 byte registers in Gameport I/O Base. Physically,

those registers are identical to Audio Base Reg30h–37h.

3.1.1.15.5 Legacy MPU401 I/O Base:

Controlled by CFG_REG44h[6], Audio Processor response

to either of two legacy MPU401 I/O address spaces. If

CFG_REG44h[6] is ‘0’, MPU401 I/O Base is 330h; if

CFG_REG44h[6] is ‘1’, MPU401 I/O Base is 300h.

There are 4 byte registers in MPU401 I/O Base. Physically,

those registers are identical to Audio Base Reg20h–23h.

LM4560 数据表(PDF) 11 Page - National Semiconductor (TI)

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LM4560 数据表(PDF) 11 Page - National Semiconductor (TI)

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