•

Channels which don’t require PCI bus cycle, i.e. cache hit

channels and I2StoMIX channel, have lower priority.

•

Channels which depend on other channel’s result, i.e.

Main Mixer Capture channel, Chorus Send channel and

Reverb Send channel, have the lowest priority.

Basically, all operation of one channel include address generation, data reading/writing, interpolation, per channel LFO, low fre-

quency FM/AM, Envelope calculation, PAN, volume adjusting and mixer accumulation. We call it Channel Operation. After all

channel’s operation are done, the mixing result will be sent to FIFO. We call this Mixing Loop.

Before each Mixing Loop, Scheduler scans cache hit/miss flags of all active channels to decide the processing sequence of the

current Loop.

4.1.2 Address Engine

Address generation, data reading/writing, per channel LFO, low frequency FM and interpolation coefficient calculation are pro-

cessed by Address Engine.

Terms:

CCI (6 bits) — Current Channel Index

CPTR (1 bit) — Cache Pointer

ESO (16 bits) — Ending Sample Offset (relative to loop begin sample)

CSO (16 bits) — Current Sample Offset (relative to loop begin sample)

CSO_SIGN (1 bit) — Sign bit of CSO

CAO (18 bits) — Current Address Offset (relative to loop begin address)

LBA (32 bits) — Loop Begin Address

CSA (32 bits) — Current Sample Address

FMS (4 bits) — Frequency Modulation Step

FMC (2 bit) — Frequency Modulation Control

SIN (4 bits) — current state of sin counter

FMA (8 bits) — Frequency Modulation Amount

BL (2 bits) — Burst read Length

DELTA (15 bits) — Sample increment number per 48 kHz clock (format 3.12)

ALPHA (12 bits) — Interpolation coefficient, i.e. fractional part of CSO

NEWCSO (16 bits) — the next CSO

NEWALPHA (12 bits) — the next ALPHA

The procedure of address engine is described as following:

(1) Load RegE0h // read FMS, CSO, ALPHA from ARAM

Load RegE4h // read LBA from ARAM

if (8 bit && MONO) CAO = CSO;

FMA = SIN*FMS;

(3) Load RegE8h // read ESO, DELTA, CPTR from ARAM

if(Cache miss)

{ // calculate address CSA = LBA + (CSO_SIGN==0) ? CAO : −CAO; // 32 bit addition }

BL is decided by CSA[1:0] and data_type[2:1];

(data_type[2:0] refers to bit[15:13] of channel register F0h)

BL

CSA[1:0]=00

CSA[1:0]=01

CSA[1:0]=10

CSA[1:0]=11

Data_type[2:1]=00

1112

Data_type[2:1]=01

1222

Data_type[2:1]=10

1222

Data_type[2:1]=11

2333

BL (Burst Length)

Update RegE8h with new CPTR

Update RegECh with new LFO_CTRL & LFO_CT

www.national.com

33