Present

State

Next

State

State Change Way

D0

D1

HIFW

D2 or

D1

D0

HIFW

Present

State

Next

State

State Change Way

D0

D2

HIFW

D2

D3

HIFW or Inactivity Timer expires

D0

D3

HIFW

5.1.2 Timing

The timing descriptions of host interface signals. All signal’s transition edges are respected to the rising edge of PCICLK. The

setup time and hold time requirements are illustrated in

Figure 4.

5.1.2.1 Slave Read/Write Timing

Slave read/write means that host performs I/O read/write operation to audio block while audio block acts as a bus slave. Data

transition occurs at the rising edge of PCICLK while both chip select signal and DATARDY are active. They are two-clock wait

states from chip select signal and DATARDY.

Timing diagram are printed into file: sl_io_rd.ps and sl_io_wr.ps .

5.1.2.2 Master Read/Write

There’s one clock wait state of IRDY which means: 1) IRDY can be asserted in 2 clocks after FRAME is asserted; 2) IRDY has

to be de-asserted for 1 clock after each of data transferring.

Timing

diagram

are

printed

into

file:

ma_mem_rd1.ps,

ma_memrd2.ps,

ma_mem_rd3.ps,

ma_mem_wr2.ps

and

ma_mem_wr3.ps.

DS100910-5

FIGURE 4. Setup Time and Hold Time of All Signals

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