| 数据搜索系统,热门电子元器件搜索 |
|
LM4560 数据表(PDF) 28 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
LM4560 数据表(HTML) 28 Page - National Semiconductor (TI) |
|
28 / 54 page ![]() 3.0 Register Description (Continued) 3.4.9.21 ST_TARGET (Sample Timer Target) Address: AudioBase + D0h Size: 32 bits Type: Read/Write Default: 00000000h Bit 31–0 (ST_TARGET) is used to store a pre-set value. Once STIMER counter reaches that value, an IRQ called ST_IRQ will be issued if ST_IRQ_En = 1. 3.4.9.22 AINT_B (Bank B Address Engine Interrupt) Address: AudioBase + D8h Size: 32 bits Type: Read/Write Default: 00000000h Any bits toggled from ‘0’ to ‘1’ will result in a IRQ. Reading from this I/O port will return the address INT status of Bank B’s 32 channels. Bit n is for channel n. 0: No INT 1: INT This bit will be set in 2 cases: When CSO (current sample offset) ≥ ESO (end sample off- set), and ENDLP_IE (end of loop INT enable bit in Global Control register) =1 and AINTEN_B bit n is set 1 for channel n. When CSO (current sample offset) ≥ ESO/2 (middle of ESO), and MIDLP_IE (middle of loop INT enable bit in Glo- bal Control register) =1 and AINTEN_B bit n is set 1 for chan- nel n. Writing ‘1’ to bit n of this register will reset this bit. 0: Ignore. A ‘0’ written to bit n will not change the status of this bit. 1: reset A ‘1’ written to bit n will reset this bit. 3.4.9.23 AINTEN_B(Bank B Address Engine Interrupt Enable) Address: AudioBase + DCh Size: 32 bits Type: Read/Write Default: 00000000h This register will control address engine interrupt for each channel of Bank B. Bit n is for channel n. 0: disable address engine interrupt for channel n 1: enable address engine interrupt for channel n 3.4.9.24 E0h (CS0 & ALPHA & FMS) (for Bank A & Bank B) This register can be accessed in index mode or direct ac- cess mode. Address: AudioBase + E0h (index mode) || Audio MEM Base + 800h + 20h*CIR (direct access mode, CIR: channel index) Size: 32 bits Type: Read/Write Default: XXXXXXXXh Description: CSO — Current Sample Offset (16 bits) ALPHA — Sample interpolation coefficient (12 bits) FMS — Frequency Modulation Step (4 bit) Bits 31–16 (CSO) is the offset of current sample relative to loop begin sample. Bits 15–4 (ALPHA) is sample interpolation coefficient, which stands for the linear interpolation ratio between current sample and the next one. Bits 3–0 (FMS) is Frequency Modulation Step. 3.4.9.25 E4h (LBA) (for Bank A & Bank B) This register can be accessed in index mode or direct ac- cess mode. Address: AudioBase + E4h (index mode) || Audio MEM Base + 804h + 20h*CIR (direct access mode, CIR: channel index) Size: 32 bits Type: Read/Write Default: XXXXXXXXh Description: Loop Begin Address (31 bits) & CPTR — Cache Pointer (1 bit) Bit 31 (CPTR) is reserved for internal use of cache control. Bits 30–0 is the linear address of loop begin sample. It should be word aligned when sample type is 16-bit Mono or 8-bit Stereo; and should be double word aligned when sample type is 16-bit Stereo. 3.4.9.26 E8h (ESO & DELTA) (for Bank A & Bank B) This register can be accessed in index mode or direct ac- cess mode. Address: AudioBase + E8h (index mode) || Audio MEM Base + 808h + 20h*CIR (direct access mode, CIR: channel index) Size: 32 bits Type: Read/Write Default: XXXXXXXXh Description: ESO — End Sample Offset (16 bits) DELTA — Sample rate ratio (16 bits) Bits 31–16 (ESO) is the offset of loop end sample relative to loop begin sample. Bits 15–0 (DELTA) is sample change step in format 4.12 (Four bits integer, 12 bits fraction), which stands for the fre- quency ratio: Fs/48 kHz, while Fs is the sum of sample rate and pitch shifting rate. 3.4.9.27 ECh_A (Bank A LFO_CTRL & LFO_CT & FMC & RVOL & CVOL) (Bank A Only) This register can be accessed in index mode or direct ac- cess mode. Address: AudioBase + ECh (index mode) || Audio MEM Base + 80Ch + 20h*CIR (direct access mode, CIR: channel index) (CIR<32) Size: 32 bits Type: Read/Write Default: XXXXXXXXh Description: LFO_CTRL — Per Channel LFO Control (8 bit) LFP_CT — Per Channel LFP working counter (8 bits) FMC — Per Channel FM control (2 bit) RVOL — Reverb Send Linear Volume (7 bit) www.national.com 28 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |