LM4560 datasheet(22/54 Pages) NSC

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3.0 Register Description (Continued)

Type:

Read/Write

Default:

3.4.7 OPL3 Channel Status Register

These 4-byte registers can only be accessed on Audio Base

(I/O or MEM).

3.4.7.1 AOPLSR0 (OPL3 Emulation Channel Key On/Off

Trace Register)

Address: AudioBase + 60h

Size:

32 bits

Type:

Read Only

Default:

00000000h

Bit 8–0

Bank0 channel 8–0 key on/off event

captured.

Bit 13–9

OPL3 rhythm channel 4–0 key

on/off event captured

Bit 14

Reserved

Bit 15

(Whichbank) Read only

Bank0

Bank1

Bit 24–26

Bank1 channel 8–0 key on/off event

captured

Bit 31–25

Reserved

All the flags will be cleared after this register is read.

3.4.8 S/PDIF & GPIO Register

This register can only be accessed on Audio Base (I/O or

MEM).

3.4.8.1 SPDIF_CS (S/PDIF Channel Status Register)

Address: AudioBase + 70h

Size:

32 bits

Type:

Read/Write

Default:

02000000h

Bit 0 (PRO) Professional flag

Hardwired to 0

Bit 1 (Audio) Audio content flag

Hardwired to 0

Bit 2 (Copy) Copyright

Read/Write, Default: 00b

Bit 5–3 (Emphasis)

Read/Write, Default: 000b

Bit 7–6 (Mode) Hardwired to 00b

Bit 15–8 (L & Category)

Read/Write, Default: 00h

Bit 19–16 (Source Num)

Read/Write, Default: 0h

Bit 23–20 (Channel Num)

Read/Write, Default: 0h

Bit 27–24(Fs) Sample rate

Hardwired to 2h (48KHz)

Bit 29–28 (Clock Acc) Clock Accuracy

Read/Write, Default: 00b

Bit 31–30 Reserved

Hardwired to 00b

3.4.8.2 GPIO (General Purpose IO Register)

Address: AudioBase + 7Ch

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Bit 31..24 reserved

Bit 23..16 GPControl[7:0]

0: Input GPI[7:0] = GP_PIN[7:0]

1: Output GP_PIN[7:0] = GPO[7:0]

Bit 15..8 GPO[7:0]

Bit 7..0 GPI[7:0]

All reserved bits return 0 when read.

3.4.9 Wave Engine Register

These 128-byte registers can be accessed on AudioBase

(Audio I/O Base or Audio MEM Base).

64 voice channels are classified into two banks.

Bank A: channel 0–31 (optimized for MIDI)

Bank B: channel 32–63 (optimized for Wave, WDM Stream,

DirectX buffer, I

2S, S/PDIF, MODEM, Handset, Recording,

Microphone, Main Mixer Capture, Reverb Send, Chorus

Send, AC97 SURR, AC97 CENTER/LFE)

Each channel in Bank A can only be programmed as a play-

back channel with individual EM (envelope modulation), indi-

vidual LFO AM and individual LFO FM.

Channels in Bank B have more flexibility. Each of them can

be programmed as a Normal PB channel with global LFO

AM and LFO FM but without EM, or as a Special PB channel,

or as a REC channel, or as a REC_PB channel. Bit[31:19] of

RegEC_B is Channel ATTIBUTE.

3.4.9.1 STAR_A (START Command and Status Register

for Bank A)

Address: AudioBase + 80h

Size:

32 bits

Type:

Read/Write

Default:

00000000h

This register and STOP_A are used as Bank A channel start/

stop command register when they are written, and used as

Bank A channel running/stopped status register when they

are read. Bit n is for channel n.

Reading from this I/O port will return the running/stopped

status of Bank A 32 voice channels.

0: Stopped.

When bit n is read as ‘0’, it means any operation of channel

n, including address generation, sample data fetching, inter-

polation, and envelope calculation is stopped. And this chan-

nel has no contribution to the digital mixer.

This bit will be reset from ‘1’ to ‘0’ in four cases.

(1) when a ‘1’ is written to the corresponding bit in register

STOP_A .

(2) when out of data, i.e. when sample loop disabled and

CSO (Current Sample Offset)

≥ ESO (End Sample Offset).

when Ec (current envelope) drops down to −63.984375 dB.

when current envelope buffer is in delay-stop mode, and

EDLY count down to ‘0’.

1: Running.

When bit n is read as ‘1’, it means channel n is working.

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