LM4560 datasheet(8/54 Pages) NSC

8 / 54 page

3.0 Register Description (Continued)

3.1.1.8 PCIPM Capability List Pointer Register:

PCI Configuration

Address:

34h–37h

Default:

000000DCh

Description: Read Only

3.1.1.9 Max_Lat, Min_Gnt, Interrupt Pin & Interrupt

Line:

PCI Configuration

Address:

3Ch–3Fh

Default:

18020100h

Description:

Bit 7–0: INT line R/W

Bit 15–8: INT pin hardwired to 01

Bit 23–16: Min_Gnt hardwired to 02

Bit 31–24: Max_Gnt hardwired to 18

3.1.1.10 DDMA Slave Configuration Register

PCI Configuration

Address: 40h–43h

Type:

Read/Write

Default:

00000000h

Bit 0: DDMA Slave Channel Access Enable Control

0 disabled

1 enabled

When disabled, the DDMABase is not usefull and the PCM

sample playback control registers cannot be accessed

through DDMA Slave channel method.

When enabled, LM4560 can behave like a DDMA Slave

channel device. DDMA Master will transfer the legacy DMA

controller channel specific information to the related DDMA

Slave channel control register when software trying to pro-

gram the legacy DMA controller register.

Bit 2..1 Legacy DMA Transfer Size Control, Read Only as 00

00 8 bit transfer, legacy

Bit 3 Non Legacy Extended Addressing Control (Fully 32 bit

Addressing)

0 disabled

1 enabled

Bit 31..4 DDMABase

3.1.1.11 Legacy audio/ power management

configuration:

PCI Configuration

Address: 44h–47h

Type:

Read/Write

Default:

E2000000h

legacy I/O decoding 44h

bit 0:

0: SBBase = 0220h–022Fh

1: SBBase = 0240h–024Fh

bit 1

0: SBBase disable

1: SBBase enable

bit 2

0: ADLIBBase = 0388h–038Bh

1: ADLIBBase = 038Ch–038Fh

bit 3

0: ADLIBBase disable

1: ADLIBBase enable

bit 4

0: GAMEBase = 0200h–0207h

1: GAMEBase = 0208h–020Fh

bit 5

0: GAMEBase disable

1: GAMEBase enable

bit 6

0: MPU401Base = 0330h–0333h

1: MPU401Base = 0300h–0303h

bit 7

0: MPU401Base disable

1: MPU401Base enable

legacy DMA decoding 45h

bit 0

0: DMA channel 1 trapping

1: DMA channel 0 trapping

bit 1

0: DMA trapping

disable 1: DMA trapping enable

bit 2

0: DMA status handle mode A (slave only)

1: DMA status handle mode B (bus master)

bit 3

0: DMA status retry OK

1: DMA status retry error

If bit 3 is set, bus interface will not respond to IO8 operation

any more unless the status retry error bit is cleared by writing

1 to this bit.

bit 4 DMAREG_RD_EN_

0: Response to DMAREG(00h–03h, 83h/87h) Read when

CFG45[1] is 1;

1: Never response to DMAREG(00h–03h, 83h/87h) Read.

bits 5–7 reserved

when DMA trapping is enable, chip will decode the following

I/O port

DMA channel 1 trapping

write snoop 2,3

write snoop 8–Fh

write snoop 83h

DMA channel 0 trapping

write snoop 0,1

write snoop 8–Fh

write snoop 87h

when DMA trapping is enable, the chip will handle DMA sta-

tus read (I/O read port 8) depending on the DMA status

mode bit.

DMA status handle mode A:

LM4560 will decode I/O read port 8 if StatusRDY is active,

otherwise, it will ignore the cycle.

DMA status handle mode B:

LM4560 数据表(PDF) 8 Page - National Semiconductor (TI)

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