L6717ATR datasheet(9/57 Pages) STMICROELECTRONICS

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L6717A

Pins description and connection diagrams

Figure 5. Pins connection (top view)

2.1

Pin descriptions

36 35 34 33 32 31 30 29 28 27 26 25

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CS1P

CS1N

CS2P

CS2N

CS3P

CS3N

CS4P

CS4N

ILIM

NB_CSP

NB_CSN

OSC / EN /FLT

BOOT1

UGATE1

PHASE1

LGATE1

LGATE2

NB_LGATE

VCCDRV

PHASE2

UGATE2

BOOT2

NB_PHASE

NB_UGATE

L6717A

PAD (GND)

Table 2. Pin description

Pin#

Name

Function

1PWROK

System-wide power good input (Ignored in PVI mode).

Internally pulled-low by 10

μA. When low, the device will decode the two SVI bits SVC

and SVD to determine the

Pre-PWROK Metal VID. When high, the device will actively

run the SVI protocol.

Pre-PWROK Metal VID are latched after EN is asserted and re-used in case of

PWROK de-assertion. Latch is reset by VCC or EN cycle.

2SGND

Device signal ground.

All the internal references are referred to this pin. Connect to the PCB signal ground.

3VCC

Device power supply.

Operative voltage is 12 ±15%. Filter with 1

μF MLCC to SGND.

COMP

CORE error amplifier output.

Connect with an R

- C

to FB.

The CORE section and/or the device cannot be disabled by grounding this pin.

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