L6717ATR datasheet(22/57 Pages) STMICROELECTRONICS

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Hybrid CPU support and CPU_TYPE detection

L6717A

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5.3

SVI - serial interface

SVI is a two wire, clock and data, bus that connects a single master (CPU) to one slave

(L6717A). The master initiates and terminates SVI transactions and drives the clock, SVC,

and the data, SVD, during a transaction. The slave receives the SVI transactions and acts

accordingly. SVI wire protocol is based on fast-mode I

SVI interface also considers two additional signal needed to manage the system start-up.

These signals are EN and PWROK. The device return a PWRGOOD signal if the output

voltages are in regulation.

5.4

SVI start-up

Once the SVI mode has been detected on the EN rising-edge, L6717A checks for the status

of the two serial VID pins, SVC and SVD, and stores this value as the

Pre-PWROK Metal

VID. The controller initiate a soft-start phase regulating both CORE and NB voltage planes

to the voltage level prescribed by the

Pre-PWROK Metal VID. See Table 7 for details about

Pre-PWROK Metal VID codifications. The stored Pre-PWROK Metal VID value are re-used

in any case of PWROK de-assertion.

After bringing the output rails into regulation, the controller asserts the PWRGOOD signal

and waits for PWROK to be asserted. Until PWROK is asserted, the controller regulates to

the

Pre-PWROK Metal VID ignoring any commands coming from the SVI interface.

After PWROK is asserted, the processor has initialized the serial VID interface and L6717A

waits for commands from the CPU to move the voltage planes from the

Pre-PWROK Metal

VID values to the operative VID values. As long as PWROK remains asserted, the controller

will react to any command issued through the SVI interface according to SVI protocol.

See

Section 7.8 for details about soft-start.

5.4.1

Set VID command

The

set VID command is defined as the command sequence that the CPU issues on the SVI

bus to modify the voltage level of the CORE Section and/or the NB section.

During a

set VID Command, the processor sends the start (START) sequence followed by

the address of the Section which the

set VID command applies. The processor then sends

the write (WRITE) bit. After the write bit, the voltage regulator (VR) sends the acknowledge

(ACK) bit. The processor then sends the VID bits code during the

data phase. The VR

sends the acknowledge (ACK) bit after the data phase. Finally, the processor sends the stop

(STOP) sequence. After the VR has detected the stop, it performs an On-the-Fly VID

Table 7. V_FIX mode and Pre-PWROK MetalVID

SVC

SVD

Output voltage [V]

Pre-PWROK Metal VID

V_FIX mode

1.1V

1.4V

1.0V

1.2V

0.9V

1.0V

0.8V

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