L6717ATR datasheet(37/57 Pages) STMICROELECTRONICS

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L6717A

Output voltage positioning

Figure 11. Current reading

The current read through the CSxP / CSxN pairs is converted into a current I

INFOx

proportional to the current delivered by each phase and the information about the average

current I

AVG

ΣI

INFOx

/ N is internally built into the device (N is the number of working

phases). The error between the read current I

INFOx

and the reference I

AVG

is then converted

into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value

is set by the voltage error amplifier in order to equalize the current carried by each phase.

7.3

CORE section - defining load-line

L6717A introduces a dependence of the output voltage on the load current recovering part

of the drop due to the output capacitor ESR in the load transient. Introducing a dependence

of the output voltage on the load current, a static error, proportional to the output current,

causes the output voltage to vary according to the sensed current.

Figure 11 shows the current sense circuit used to implement the load-line. The current

flowing across the inductor(s) is read through the R - C filter across CSxP and CSxN pins.

programs a trans-conductance gain and generates a current I

CSx

proportional to the

current of the phase. The sum of the I

CSx

current, with proper gain defined by the DRP_ADJ

command (k

DRP

), is then sourced by the FB pin (k

DRP

DROOP

). R

gives the final gain to

program the desired load-line slope (

Figure 10).

Time constant matching between the inductor (L / DCR) and the current reading filter (RC) is

required to implement a real equivalent output impedance of the system so avoiding over

and/or under shoot of the output voltage as a consequence of a load transient. See

Section 7.2. The output characteristic vs. load current is then given by:

Where R

is the resulting load-line resistance implemented by the CORE section. k

DRP

value is determined by the power manager I

C and its default value is 1/4.

resistor can be then designed according to the R

specifications and DRP_ADJ setting

as follow:

See

Section 6.2 for details about DRP_ADJ command.

CSxN

CSxP

DCR

PHASEx

Inductor DCR Current Sense

CSxN

INFOx

OUT

CO R E

VID

DR P

DR OOP

⋅⋅

–

VI D

DR P

DC R

------------- I

OU T

⋅⋅

⋅

–

VI D

OU T

⋅

–

DR P

-------------

DC R

-------------

⋅

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