L6717ATR datasheet(19/57 Pages) STMICROELECTRONICS

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L6717A

Device description and operation

L6717A is a hybrid CPU power supply controller compatible with both parallel (PVI) and

serial (SVI) protocols for AMD processors. The device provides complete control logic and

protections for a high-performance step-down DC-DC voltage regulator, optimized for

advanced microprocessor power supply supporting both PVI and SVI communication. It

embeds two independent controllers for CPU CORE and the integrated NB, each one with

its own set of protections. NB phase (when enabled) is automatically phase-shifted with

respect to the CORE phases in order to reduce the total input rms current amount.

The device features an additional power manager I

C interface to easy the system design

for enthusiastic application where the main parameters of the voltage regulator have to be

modified. L6717A is able to adjust the regulated voltage, the switching frequency and also

the OV protection threshold through the power manager I

C bus while the application is

running assuring fast and reliable transitions.

Dynamic phase management (DPM) allows the device to automatically adjust the phase

count according to the current delivered to the load. This feature allow the system to keep

alive only the phases really necessary to sustain the load saving in power dissipation so

optimizing the efficiency over the whole current range of the application. DPM can be

enabled through the power manager I

C bus.

L6717A is able to detect which kind of CPU is connected in order to configure itself to work

as a single-plane PVI controller or dual-plane SVI controller.

The controller performs a single-phase control for the NB section and a programmable 2-to-

4 phase control for the CORE section featuring dual-edge non-latched architecture: this

allows fast load-transient response optimizing the output filter consequently reducing the

total BOM cost. Further reduction in output filter can be achieved by enabling LTB

Technology

PSI_L Flag is sent to the VR through the SVI bus. The controller monitors this flag and

selectively modifies the phase number in order to optimize the system efficiency when the

CPU enters low-power states. This causes the over-all efficiency to be maximized at light

loads so reducing losses and system power consumption.

Both sections feature programmable overvoltage protection and adjustable constant

overcurrent protection. Voltage positioning (LL) is possible thanks to an accurate fully-

differential current-sense across the main inductors for both sections.

L6717A features dual remote sensing for the regulated outputs (CORE and NB) in order to

recover from PCB voltage drops also protecting the load from possible feedback network

disconnections.

LSLess start-up function allows the controller to manage pre-biased start-up avoiding

dangerous current return through the main inductors as well as negative undershoot on the

output voltage if the output filter is still charged before start-up.

L6717A supports V_FIX mode for system debugging: in this particular configuration the SVI

bus is used as a static bus configuring 4 operative voltages for both the sections and

ignoring any serial-VID command.

When working in PVI mode, the device features On-the-Fly VID management: VID code is

continuously sampled and the reference update according to the variation detected,

L6717A is available in VFQFPN48 package.

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