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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITEUS5 数据表(PDF) 56 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 56 Page - STMicroelectronics |
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56 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Power saving modes ST7LITEUS2, ST7LITEUS5 56/136 Figure 27. AWUFH mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 9: Interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. RESET INTERRUPT 3) Y N N Y CPU MAIN OSC PERIPHERALS 2) I[1:0] BITS OFF OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU MAIN OSC PERIPHERALS I[1:0] BITS ON OFF XX 4) ON CPU MAIN OSC PERIPHERALS I[1:0] BITS ON ON XX 4) ON 64 CPU CLOCK DELAY WATCHDOG ENABLE DISABLE WDGHALT 1) 0 WATCHDOG RESET 1 CYCLE AWU RC OSC ON AWU RC OSC OFF AWU RC OSC OFF HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) Obsolete Product(s) - Obsolete Product(s) |
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