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ST7LITEUS5 数据表(PDF) 73 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals 73/136 Figure 35. PWM signal example Output compare mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H and DCR0L registers. This value will be loaded immediately (without waiting for an OVF event). The DCR0H must be written first, the output compare function starts only when the DCR0L value is written. When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated if the CMPIE bit is set. Note: The output compare function is only available for DCRx values other than 0 (reset value). Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value has not yet been written (in this case, the shadow register will contain the new DCR0H value and the old DCR0L value), then: – If OE=1 (PWM mode): the compare is done between the timer counter and the shadow register (and not DCRx) – If OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There is no PWM signal. The compare between DCRx or the shadow register and the timer counter is locked until DCR0L is written. 10.2.4 Low power modes COUNTER t FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh DCR0=FFEh ATR= FFDh fCOUNTER Table 27. Description of low power modes Mode Description Slow The input frequency is divided by 32 Wait No effect on AT timer Active-halt AT timer halted except if CK0=1, CK1=0 and OVFIE=1 Halt AT timer halted Obsolete Product(s) - Obsolete Product(s) |
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