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ST7LITEUS5 数据表(PDF) 38 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 38 Page - STMicroelectronics |
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38 / 136 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Supply, reset and clock management ST7LITEUS2, ST7LITEUS5 38/136 This 16-bit register is read/write by software but can be written only once between two reset events. It is cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. These registers are one-time writable only. ● To configure PA3 as general purpose output: After power-on / reset, the application program has to configure the I/O port by writing to these registers as described above. Once the pin is configured as an I/O output, it cannot be changed back to a reset pin by the application code. ● To configure PA3 as RESET: An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear the two registers and the pin will act again as a reset function. Otherwise, a power-down is required to put the pin back in reset configuration. Table 8. Multiplexed IO register map and reset values Address (Hex.) Register label 765432 10 0047h MUXCR0 reset value MIR7 0 MIR6 0 MIR5 0 MIR4 0 MIR3 0 MIR2 0 MIR1 0 MIR0 0 0048h MUXCR1 reset value MIR15 0 MIR14 0 MIR13 0 MIR12 0 MIR11 0 MIR10 0 MIR9 0 MIR8 0 Obsolete Product(s) - Obsolete Product(s) |
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