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ST7LITEUS5 数据表(PDF) 67 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 67 Page - STMicroelectronics |
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67 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals 67/136 A watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit has to be set. The WDGRF bit also acts as a flag, indicating that the watchdog was the source of the reset. It is automatically cleared after it has been read. Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the microcontroller will be immediately reset. Hardware watchdog option If hardware watchdog is selected by option byte, the watchdog is always active and the WDGE bit in the LTCSR is not used. Refer to the option byte description in the "device configuration and ordering information" section. Using Halt mode with the watchdog (option) If the watchdog reset on Halt option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite Timer stops counting and is no longer able to generate a watchdog reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks. If a reset is generated, the watchdog is disabled (reset state). If Halt mode with watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. Figure 31. Watchdog timing diagram Input capture The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the MSB of the free-running upcounter. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set. tWDG fWDG INTERNAL WATCHDOG RESET WDGD BIT SOFTWARE SETS WDGD BIT HARDWARE CLEARS WDGD BIT WATCHDOG RESET (2ms @ 8 MHz fOSC) Obsolete Product(s) - Obsolete Product(s) |
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