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ST7LITEUS5 数据表(PDF) 77 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 77 Page - STMicroelectronics |
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77 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals 77/136 PWM0 control/status register (PWM0CSR) Reset value: 0000 0000 (00h) PWM output control register (PWMCR) Reset value: 0000 0000 (00h) 7 0 00 00 00 OP0 CMPF0 Read/Write Bit 7:2 Reserved, must be kept cleared. Bit 1 OP0 PWM0 output polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal. 0: The PWM0 signal is not inverted. 1: The PWM0 signal is inverted. Bit 0 CMPF0 PWM0 Compare Flag. This bit is set by hardware and cleared by software by reading the PWM0CSR register. It indicates that the upcounter value matches the DCR0 register value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value. 7 0 00 00 00 0 OE0 Read/Write Bits 7:1 Reserved, must be kept cleared. Bit 0 OE0 PWM0 Output enable. This bit is set and cleared by software. 0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O) 1: PWM0 output enabled Table 30. Register map and reset values Address (Hex.) Register label 76 5432 10 0D ATCSR Reset value 00 0 CK1 0 CK0 0 OVF 0 OVFIE 0 CMPIE 0 0E CNTRH Reset value 00 00 CN11 0 CN10 0 CN9 0 CN8 0 0F CNTRL Reset value CN7 0 CN6 0 CN5 0 CN4 0 CN3 0 CN2 0 CN1 0 CN0 0 10 ATRH Reset value 00 00 ATR11 0 ATR10 0 ATR9 0 ATR8 0 Obsolete Product(s) - Obsolete Product(s) |
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